Chip arrangement determining apparatus and method

Details Chip arrangement determining apparatus and method Chip arrangement determining apparatus and method

2005-02-08

2005-02-08

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06854105

ABSTRACT:
A method for determining a chip arrangement on a wafer. The method includes steps of generating a grid array in which rectangles are arranged in a grid pattern, the rectangle corresponding to a chip in size, an apex of the rectangle being a grid point, extracting a plurality of the grid points, having respective distances, from an origin, not greater than a constant defined by an available area on the wafer, from the grid array, forming a region, of which a form corresponds to the available area and which has the original and one of the extracted grid points on its circumference, on the grid array, with respect to each of the plurality of the grid points extracted in the extracting step, and determining a chip arrangement on the wafer based on a region, which includes a maximum number of the rectangles, formed in the forming step.

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patent: 6546543 (2003-04-01), Manabe et al.
patent: 20020111038 (2002-08-01), Matsumoto et al.
patent: 20030224557 (2003-12-01), Koduri et al.
patent: 2000-195824 (2000-07-01), None

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