Chip-area reduction and congestion alleviation by...

Details Chip-area reduction and congestion alleviation by... Chip-area reduction and congestion alleviation by...

2007-04-03

2007-04-03

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10843791

ABSTRACT:
An EDA (Electronic Design Automation) process which collects and moves empty-spaces among cells on a circuit layout to one or more target areas for productive use, such as chip-size reduction and routability congestion alleviation. The process includes globally moving the empty-spaces to the target area and thereafter locally moving the empty-spaces as refinement.

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