Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-09-21
2001-10-23
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S598000
Reexamination Certificate
active
06306745
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method and pattern for routing power and ground for an integrated circuit chip.
(2) Description of the Related Art
Distribution of a power supply voltage and a reference voltage to an integrated circuit chip is a key part of the chip wiring layout design. Voltages must be distributed to all parts of the chip within strict voltage drop tolerances. Capacitance between the electrodes supplying the power and reference voltages can also be an important consideration.
U.S. Pat. No. 6,025,616 to Nguyen et al. describes a power distribution system for a semiconductor die which includes bonding pads located adjacent to and connected to power busses with connections to the bonding pads providing a parallel path for current.
U.S. Pat. No. 5,949,098 to Mori describes a semiconductor integrated circuit having a power wiring layer and a ground wiring layer with an insulating layer between the power and ground layers.
U.S. Pat. No. 5,313,079 to Brasen et al. describes gate arrays having functional blocks with flexible power routing.
U.S. Pat. No. 5,517,042 to Kitamura describes a semiconductor device having first and second device regions, a first power supply region, and a second power supply region.
SUMMARY OF THE INVENTION
With large chips and dense circuitry becoming common it is important to provide power and ground routing which will make very efficient use of chip area, reduce voltage drops due to electrode resistance, and provide decoupling capacitance between the power and ground supply electrodes.
Currently the general practice in routing the top level power and ground is to form the power and ground electrodes from the same metal layer. While more than one metal layers may be used to distribute power and ground, each metal layer has both power and ground electrodes. This conventional arrangement is shown in
FIGS. 1-3
.
FIG. 1
shows a composite top view of a chip
10
having a circuit region
29
partitioned into five separate sub-blocks, sub-block A
18
, sub-block B
20
, sub-block C
22
, sub-block D
24
, and sub-block E
26
. The chip
10
has a peripheral region
12
for input output tabs, not shown. The chip has a power bus
14
and a ground bus
16
.
FIG. 1
is a composite top surface view showing the wiring for two separate metal layers. The electrodes in the horizontal direction are in one metal layer and the electrodes in the vertical direction are in another wiring layer. The inter layer contacts for the power bus
14
are shown as darkened regions
28
. The inter layer contacts for the ground bus are also shown as darkened regions
30
.
FIG. 2
shows the metal layer having the power bus electrodes
14
H and the ground bus electrodes
16
H in the horizontal direction.
FIG. 3
shows the metal layer having the power bus electrodes
14
V and the ground bus electrodes
16
V in the vertical direction.
This arrangement results in power and ground routed in parallel electrodes in the same metal which restricts the width of the power and ground busses and provides very little decoupling capacitance between the power and ground electrodes. For large chips and dense circuitry the current practice results in significant voltage drop due to the resistance of long power and ground electrodes and insufficient decoupling capacitance between power and ground electrodes.
It is a principle objective of this invention to provide a method of routing power and ground wiring which makes efficient use of chip area, reduces voltage drops due to electrode resistance, and provides increased decoupling capacitance between power and ground electrodes.
It is another principle objective of this invention to provide a power and ground wiring layout which makes efficient use of chip area, reduces voltage drops due to electrode resistance, and provides increased decoupling capacitance between power and ground electrodes.
These objectives are achieved by using the two top wiring layers as power distribution layers to distribute the power supply voltage, such as V
DD
, and reference voltage, such as ground or V
SS
, so the power supply voltage bus electrode and the reference voltage bus electrode are on separate wiring levels. The power supply voltage bus electrode and the reference voltage bus electrode are in adjacent wiring layers and in the same location on the chip so that decoupling capacitance between the power supply voltage bus electrode and reference voltage bus electrode is maximized. Since the power supply voltage bus electrode and the reference voltage bus electrode are in separate wiring layers the width of these electrodes can be maximized to reduce the voltage drop due to the resistance of the electrodes.
REFERENCES:
patent: 5313079 (1994-05-01), Brasen et al.
patent: 5358886 (1994-10-01), Yee et al.
patent: 5517042 (1996-05-01), Kitamura
patent: 5801091 (1998-09-01), Efland et al.
patent: 5949098 (1999-09-01), Mori
patent: 6025616 (2000-02-01), Nguyen et al.
Ackerman Stephen B.
Elms Richard
Prescott Larry J.
Saile George O.
Smith Bradley
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