Chip and wafer integration process using vertical connections

Details Chip and wafer integration process using vertical connections Chip and wafer integration process using vertical connections

2005-02-15

2005-02-15

Thai, Luan (Department: 2829)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S621000, C257S773000, C257S736000

Reexamination Certificate

active

06856025

ABSTRACT:
A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

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U.S. Appl. No. 09/669,531, filed Sep. 26, 2000 entitled “Process for making fine pitch connections between devices and structure made by the process” Pogge et al.

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