Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1998-06-29
2001-04-03
Whitehead, Jr., Carl (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000, C438S693000, C438S747000, C438S751000
Reexamination Certificate
active
06211087
ABSTRACT:
BACKGROUND
The present invention concerns the fabrication of integrated circuits and pertains particularly to the wet etch removal of underlayer material after performing chemical mechanical polishing on a primary layer.
The trend in integrated circuit manufacturing is to increase the amount of circuitry within each individual integrated circuit. Along with this trend there is an increase in the number of layers used and a decrease in the dimensions of the patterned layers.
As the pattern dimensions within integrated circuits shrink in size, it is necessary to provide more accurate methods to accurately and uniformly perform the processing steps.
When processing integrated circuits, masks are utilized to pattern and etch layers of material deposited on a wafer. These layers are composed of, for example, polysilicon, metal or oxide.
As optical resolution increases, the depth of focus of the mask image correspondingly narrows. This is due to the narrow range in depth of focus imposed by the high numerical aperture lenses in photolithography tools which use the mask images. This narrowing depth of focus is often the limiting factor in the degree of resolution obtainable, and thus, the smallest components obtainable using the photolithography. Unevenness in the surface of a wafer exaggerate the effects of decreasing depth of focus. Thus, in order to properly focus the mask image defining sub-micron geometries, a precisely flat (i.e. fully planarized) surface is desired. A fully planarized surface will allow for a small depth of focus, thus aiding in the definition and subsequent fabrication of extremely small components.
Chemical-mechanical polishing (CMP) is generally used to aid in planarization of a wafer. When performing CMP, a sacrificial layer of dielectric material is removed using mechanical contact between a wafer and a moving polishing pad saturated with slurry. Polishing flattens out height differences, and thus planarizes the topography of a wafer.
CMP is widely accepted as the preferred process for planarizing dielectric materials and metal plugs placed on a wafer. This is particularly true when the technology uses dimensions on the order of 0.25 micrometers or smaller. Slurry used in such a CMP process generally includes two parts. The first part is a pH-controlled chemical solution. The second part is an abrasive.
For example, during CMP-based dielectric planarization, the chemical solution may be an aqueous alkaline solution which depolymerizes the glass surface forming soft hydroxides. This chemical solution is used by the abrasive action of colloidal silica particles in the slurry. For additional information on this process, see L. Cook,
Journal of Noncrystalline Solids
, 120,152 (1990).
In metal CMP processes, slurries help to form soft abradable metal oxides which can easily be removed by the mechanical action of the abrasives in suspension. Slurries are typically targeted to remove one particular film and further optimized to remove other secondary films (exposed during CMP) at a certain removal rate (RR). A low removal rate is used if it is desired to stop on the film. A high removal rate is used if polishing of the film is desired.
However, given the many competing requirements for a particular slurry, it may not be feasible to meet the requirement of easily removing secondary films. In such cases, the polishing step is increased in time (which can significantly degrade throughput) or the layer is left behind and removed subsequently during metal etch (but this adds to the metal stack height and the complexity of metal etch). Either solution impacts wafer processing throughput and thus increases the cost of the process.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, a method is presented for planarizing a primary layer deposited over a secondary layer. A chemical mechanical polishing process is performed using a slurry which targets the primary layer. Then, chemical etching is performed using a chemical wet etchant which targets the secondary layer.
For example, the method is used when making connections to a lower layer through an insulating layer. Plug holes are formed through the insulating layer to the lower layer. Then the secondary layer is deposited. The secondary layer acts as a barrier layer or a glue layer. The primary layer is deposited over the barrier layer. The chemical mechanical polishing process is performed using the slurry which targets the primary layer. Also, the chemical etching is performed which uses the chemical wet etchant which targets the barrier layer.
For example, the primary layer is Tungsten and the secondary layer is Titanium or Titanium Nitride. The chemical wet etchant includes, for example, hydrogen peroxide, and the slurry includes Ferric Nitrate Alumina.
The present invention is most effective when the primary layer is at least five times thicker than the secondary layer and the chemical wet etchant has a removal rate of the primary layer which is lower than the removal rate of the secondary layer.
The present invention allows for an effective method for planarization of a primary layer deposited over a secondary, thinner layer. The present invention decreases the polishing time and thus reduces the erosion in the surrounding oxide and exposed Tungsten layers. The etching on a polisher, as discussed herein, reduces the amount of chemicals required as the combination of down force and contact with a pad improves the etch rate of Titanium and Titanium Nitride
REFERENCES:
patent: 5682055 (1997-10-01), Huang et al.
patent: 5789360 (1998-08-01), Song et al.
patent: 5889328 (1999-03-01), Joshi et al.
patent: 5976982 (1999-11-01), Levy et al.
patent: 6001730 (1999-12-01), Farkas et al.
Gabriel Calvin
Weling Milind
Berezny Neal
Jr. Carl Whitehead
VLSI Technology Inc.
Weller Douglas L.
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