Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-04-13
2001-06-05
Mintel, William (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S310000, C257S315000, C257S316000, C257S410000, C257S411000, C365S145000, C365S177000
Reexamination Certificate
active
06242771
ABSTRACT:
BACKGROUND OF THE INVENTION
This application relates to ferroelectric thin films which are used in nonvolatile memories and specifically to a C-axis oriented ferroelectric used in a metal-ferroelectric-metal-silicon semi-conductor. Known ferroelectric random access memories (FRAM) are constructed with one transistor (1T) and one capacitor (1C). The capacitor is generally made by sandwiching a thin ferroelectric film between two conductive electrodes, which electrodes are usually made of platinum. The circuit configuration and the read/write sequence of this type of memory are similar to that of conventional dynamic random access memories (DRAM), except that no data refreshing is necessary in a FRAM. Known FRAM devices, however, have a fatigue problem that has been observed in the ferroelectric capacitor, which is one of the major obstacles that limits the viable commercial use of such memories. The fatigue is the result of a decrease in the switchable polarization (stored nonvolatile charge) that occurs with an increased number of switching cycles. As used in this case, “switching cycles” refers to the sum of reading and writing pulses in the memory.
Another known use of ferroelectric thin films in memory applications is to form a ferroelectric-gate-controlled field effect transistor (FET) by depositing the ferroelectric thin film directly onto the gate area of the FET. Such ferroelectric-gate controlled devices have been known for some time and include devices known as metal-ferroelectric-silicon (MFS) FETs. FRAMs incorporating the MFS FET structure have two major advantages over the transistor-capacitor configuration: (1) The MFS FET occupies less surface area, and (2) provides a non-destructive readout (NDR). The latter feature enables a MFS FET device to be read thousands of times without switching the ferroelectric polarization. Fatigue, therefore, is not a significant concern when using MFS FET devices. Various forms of MFS FET structures may be constructed, such as metal ferroelectric insulators silicon (MFIS) FET, metal ferroelectric metal silicon (MFMS) FET, and metal ferroelectric metal oxide silicon (MFMOS) FET.
There are a number of problems that must be overcome in order to fabricate an efficient MFS FET device. The first problem is that it is difficult to form an acceptable crystalline ferroelectric thin film directly on silicon. Such structure is shown in U.S. Pat. No. 3,832,700. Additionally, it is very difficult to have a clean interface between the ferroelectric material and the silicon. Further, there is a problem retaining an adequate charge in the ferroelectric material. A ferroelectric memory (FEM) structure on a gate region is shown in U.S. Pat. No. 5,303,182, which emphasizes that the transfer of metal ions into the gate region is undesirable. Similar structure is shown in U.S. Pat. No. 5,416,735.
Film deposition techniques may be broadly classified as physical vapor deposition (PVD) and chemical processes. The chemical processes may further be broken down into chemical vapor deposition (CVD) and wet chemical processes, including sol-gel and metalorganic decomposition (MOD).
Physical vapor deposition (PVD), has the advantages of (1) dry processing, (2) high purity and cleanliness, and (3) compatibility with semiconductor integrated circuit processing. PVD results in a Pb
5
Ge
3
O
11
layer that (1) has low throughput, (2) has poor step coverage, and (3) may require high-temperature, post-deposition annealing, and which, in the case of complicated compounds, suffers from difficult stoichiometric control. PVD techniques include electron-beam evaporation, RF diode sputtering, RF magnetron sputtering, DC magnetron sputtering, ion beam sputtering, molecular beam epitaxy and laser ablation.
Sol-gel and MOD processes may be used, as these are simple processes, that provide molecular homogeneity, good composition control and low capital costs. However, these processes frequently result in film cracking when used for FE thin film formation because of large volume shrinkage during post deposition annealing.
SUMMARY OF THE INVENTION
The method of the invention for forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon includes: forming a silicon device area for the FEM gate unit; implanting doping impurities of a first type in the silicon device area to form a conductive channel of a first type for use as a source junction region and a drain junction region; forming a conductive channel of a second type to act as a gate junction region between the source junction region and drain junction region for the FEM gate unit on the silicon device area; depositing an FEM gate unit over the gate junction region, including depositing a lower electrode, depositing a c-axis oriented Pb
5
Ge
3
O
11
FE layer by chemical vapor deposition (CVD), and depositing an upper electrode, wherein the FEM gate unit is sized on the gate junction region such that any edge of the FEM gate unit is a distance “D” from the edges of the source junction region and the drain junction region, where “D” is between about 50 nm and 300 mn; and depositing an insulating structure about the FEM gate unit.
A ferroelectric memory (FEM) cell of the invention includes: a single-crystal silicon substrate including an active region therein; a source junction region and a drain junction region located in the active region, doped with doping impurities of a first type to form a pair of conductive channels of a first type; a gate junction region located in the active region between the source junction region and the drain junction region, doped to form a conductive channel of a second type; a FEM gate unit including a lower electrode, a c-axis oriented Pb
5
Ge
3
O
11
FE layer formed by CVD and an upper electrode; wherein the FEM gate unit is sized on the gate junction region such that any edge of the FEM gate unit is a distance “D” from the edges of the source junction region and the drain junction region, where “D” is between about 50 nm and 300 nm; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and a source electrode and a drain electrode, each located on the upper surface of the insulating layer and extending therethrough to make electrical contact with their respective junction regions, and a gate electrode located on the upper surface of the insulating layer and extending therethrough to make electrical contact with the upper electrode of the FEM gate unit.
An object of the invention is to manufacture a MFS FET device which incorporates c-axis FE material deposited by chemical vapor deposition.
Another object of the invention is to provide a method of reliable chemical vapor deposition for making c-axis FE lead germanate thin films.
Another object of the invention is to provide an MFS FET device which provides a non-destructive readout.
Yet another object of the invention to provide an MFS FET device that occupies a relatively small surface area.
A further object of the invention is to provide an MFS FET device which requires a relatively low programming voltage.
These and other objects and advantages of the invention will become more fully apparent as the description which follows is read in conjunction with the drawings.
REFERENCES:
patent: 3832700 (1974-08-01), Wu et al.
patent: 5204314 (1993-04-01), Kirlin et al.
patent: 5303182 (1994-04-01), Nakao et al.
patent: 5416735 (1995-05-01), Onishi et al.
patent: 6011285 (2000-01-01), Hsu et al.
Lee et al. Processing of a Uniaxial Ferroelectric Pb5Ge3O11Thin-Film at 450°C with C-Axis Orientation, 1992.*
GoAppl. Phys. Lett., pp. 2487-2496, (1992).*
Article entitled “Oriented Lead Germanate Thin Films by Excimer Laser Ablation” by C.J. Peng, D. Roy and S.B. Krupanichi, published in Apple. Phys. Letter 60(7), Feb. 17, 1992, pp. 827-829.
Article entitled “Study on Ferroelectric Thin Films for Application to NDRO Non-volatile Memories”, by Y. Nakao, T. Nakamura, A. Kamisawa, H. Takasu, published in Integrated Ferroelectrics, 1995,
Hsu Sheng Teng
Lee Jong Jan
Peng Chien Hsiung
Babdau Matthew D.
Krieger Scott C.
Mintel William
Ripma David C.
Sharp Laboratories of America Inc.
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