Chemical vapor deposition methods of forming a high K...

Coating processes – Electrical product produced – Condenser or capacitor

Reexamination Certificate

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C427S576000, C427S081000, C427S126300, C427S255190, C427S255310, C427S255360, C427S255391, C427S419200, C438S381000, C438S763000

Reexamination Certificate

active

06335049

ABSTRACT:

TECHNICAL FIELD
This invention relates to chemical vapor deposition methods of forming a high K dielectric layer and to methods of forming a capacitor.
BACKGROUND OF THE INVENTION
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell structure are important. The feature size of 256 Mb DRAMs and beyond will be on the order of 0.25 micron or less, and conventional dielectrics such as SiO
2
and Si
3
N
4
might not be suitable because of small dielectric constants.
Highly integrated memory devices, such as 256 Mbit DRAMs, are expected to require a very thin dielectric film for the 3-dimensional capacitor of cylindrically stacked or trench structures. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO
2
equivalent thickness.
Insulating inorganic metal oxide materials (such as ferroelectric materials, perovskite materials and pentoxides) are commonly referred to as “high k” materials due to their high dielectric constants, which make them attractive as dielectric materials in capacitors, for example for high density DRAMs and non-volatile memories. In the context of this document, “high k” means a material having a dielectric constant of at least 20. Such materials include tantalum pentoxide, barium strontium titanate, strontium titanate, barium titanate, lead zirconium titanate and strontium bismuth tantalate. Using such materials enables the creation of much smaller and simpler capacitor structures for a given stored charge requirement, enabling the packing density dictated by future circuit design.
SUMMARY
The invention comprises chemical vapor deposition methods of forming a high K dielectric layer and methods of forming a capacitor. In one implementation, a chemical vapor deposition method of forming a high k dielectric layer includes positioning a substrate within a chemical vapor deposition reactor. At least one metal comprising precursor and N
2
O are provided within the reactor under conditions effective to deposit a high k dielectric layer on the substrate comprising oxygen and the metal of the at least one metal precursor. The N
2
O is present within the reactor during at least a portion of the deposit at greater than or equal to at least 90% concentration by volume as compared with any O
2
, O
3
, NO, and NO
X
injected to within the reactor. In one implementation, the conditions are void of injection of any of O
2
, O
3
, NO, and NO
X
to within the reactor during the portion of the deposit.
In one implementation, a method of forming a capacitor includes forming a first capacitor electrode layer over a substrate. The substrate with the first capacitor electrode layer is positioned within a chemical vapor deposition reactor. At least one metal comprising precursor and N
2
O are provided within the reactor under conditions effective to deposit a high k capacitor dielectric layer comprising oxygen and the metal of the at least one metal precursor over the first capacitor electrode. The N
2
O is present within the reactor during at least a portion of the deposit at greater than or equal to at least 90% concentration by volume as compared with any O
2
, O
3
, NO, and NO
X
injected to within the reactor to form an outermost surface of the capacitor dielectric layer at conclusion of the portion to have a roughness of no greater than 20 Angstroms as determinable by average atomic force microscopy RMS roughness. A second capacitor electrode layer is formed over the high k capacitor dielectric layer.
In preferred implementations, the technique can be used to yield smooth, continuous dielectric layers in the absence of haze or isolated island-like nuclei.


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