Compositions – Etching or brightening compositions
Reexamination Certificate
2001-04-05
2003-04-01
Goudreau, George (Department: 1763)
Compositions
Etching or brightening compositions
C252S079200, C252S079300, C252S079400
Reexamination Certificate
active
06540935
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to chemical/mechanical polishing (CMP) of microelectronic devices, and more particularly, the present invention relates to CMP slurries and to fabrication processes employing CMP slurries.
2. Description of the Related Art
As the degree of integration of microelectronic devices continues to increase, planarization processes used in the fabrication of such devices become more and more critical. That is, efforts to achieve highly integrated semiconductor devices are typically attended by the stacking of multiple interconnection and other layers on a semiconductor wafer. The resultant unevenness of the wafer surface presents a variety of problems which are well-documented in the art. Planarization processes are thus adopted at various stages of fabrication in an effort to minimize irregularities in the wafer surface.
One such planarization technique is chemical/mechanical polishing (CMP). In CMP, the wafer surface is pressed against a polishing pad in relative rotation. During polishing, an abrasive and chemically reactive solution known as a CMP slurry is made to flow into the polishing pad. This CMP technique planarizes the wafer surface by means of chemical and physical reactions, that is, by supplying the chemically reactive slurry on a patterned surface of the wafer while at the same time physically pressing the relative rotating surface of the polishing pad against the surface of the wafer.
FIG. 1
is a schematic diagram showing a conventional example of a CMP apparatus used in the manufacture semiconductor devices. The illustrated CMP apparatus includes a polishing head
102
, a polishing table
104
, a slurry supply line
106
and a polishing pad
108
. The CMP process is carried out on the polishing table
104
, having the polishing pad
108
formed thereon. That is, while a slurry is supplied from a slurry supply line
106
, the polishing head
102
is made to rotate while pressing the substrate
100
against the polishing pad
108
. In this manner, polishing is achieved.
One common application of CMP is in shallow trench isolation (STI). In STI techniques, relatively shallow isolation trenches are formed, which function as field regions used to separate active regions on a wafer. A conventional example of an STI process is shown in FIGS.
2
(
a
)-
2
(
d
). In this process, a pad oxide layer
202
and a silicon nitride (SiN) stop layer
204
are sequentially stacked on a semiconductor substrate
200
. Thereafter, a photoresist pattern (not shown) is formed atop the SiN stop layer
204
. Then, using the photoresist as a mask, the SiN stop layer
204
, pad oxide layer
202
and the semiconductor substrate
200
are partially etched to form a plurality of trenches
206
as shown in FIG.
2
(
a
). Subsequently, as shown in FIG.
2
(
b
), an insulating oxide layer
208
(which will ultimately form the trench oxide regions) is deposited so as to fill the trenches
206
and cover the surface of the SiN stop layer
204
. The oxide layer
208
is then subjected to CMP so as to remove the oxide layer
208
down to the level of the SiN stop layer
204
. As a result, the configuration of FIG.
2
(
c
) is obtained. The SiN stop layer
204
and the pad oxide layer
202
on the active regions are then removed via an etching process. Thereafter, a gate oxide layer
210
is formed on the surface of the semiconductor substrate
200
as shown in FIG.
2
(
d
).
During the first-mentioned CMP process, the oxide layer
208
is removed until the upper surface of the SiN stop layer
204
is exposed. Due to differing chemical and physical characteristics thereof, the oxide and SiN layers exhibit different removal rates when subjected to CMP using known slurries. The ratio of these removal rates at least partially defines the “selectivity” of the slurry being used. The lower the selectivity of the slurry, the more SiN that will be polished away during the CMP process.
Ideally, the CMP process would not remove any of the SiN layer, i.e., the selectivity would be infinite. However, present CMP slurries exhibit low selectivity (about 4 to 1, oxide to SiN), and thus polish the SiN layer at unacceptably high rates. As a result, the SiN patterns may be irregularly removed during the CMP process, whereby thicknesses of the SiN patterns may vary across the wafer. This is especially problematic in the case where the semiconductor substrate has both densely and sparsely distributed patterns on the surface thereof. The end result is step differences between the active and field regions when the formation of the field regions is complete. This can adversely affect subsequent device fabrication, which in turn can degrade transistor and device characteristics, thus reducing process margins.
Hence, in the STI process, it is desirable that the SiN layer patterns have uniform thicknesses after removal of the oxide layer by CMP. However, uniformly thick SiN patterns are extremely difficult to achieve since present CMP slurries do not exhibit sufficient selectivity between the oxide and SiN layers.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a CMP slurry which exhibits improved removal selectivity between oxide and silicon nitride layers.
It is a further object of the present invention to provide a CMP process which exhibits improved removal selectivity between oxide and silicon nitride layers.
It is still a further object of the present invention to provide an STI process which utilizes a CMP process having high removal selectivity between oxide and silicon nitride layers.
According to one aspect of the invention, a CMP slurry is provided which includes an aqueous solution containing abrasive particles and two or more different passivation agents. Preferably, the aqueous solution is made up of deionized water, and the abrasive particles are a metal oxide selected from the group consisting of ceria, silica, alumina, titania, zirconia and germania. Also, a first passivation agent may be an anionic, cationic or nonionic surfactant, and a second passivation agent may be a phthalic acid. In one example, the first passivation agent is poly-vinyl sulfonic acid, and the second passivation agent is potassium hydrogen phthalate.
The aqueous solution forming the CMP slurry may also include a removal rate accelerator, such as ammonium hydrogen phosphate. The aqueous solution may further include a pH controller for controlling a pH thereof.
In another aspect of the invention, a CMP method is provided in which a surface of a semiconductor wafer is made to contact a surface of a polishing pad, an aqueous solution containing abrasive particles and different first and second passivation agents is supplied to an interface between the surface of the polishing pad and the surface of the semiconductor wafer, and the surface of the semiconductor wafer is made to rotate relative to the surface of the polishing pad.
In still another aspect of the present invention, an STI method is provided in which a pad oxide layer and a silicon nitride layer are sequentially formed over a surface of a semiconductor substrate, a plurality of trenches are formed through the silicon nitride layer and the pad oxide layer and into the semiconductor substrate, an insulating oxide layer is formed within the plurality of trenches and over the silicon nitride layer, the insulating oxide layer is subjected to CMP so as to remove the insulating oxide layer down to a level of silicon nitride layer, and the pad oxide layer and the silicon nitride layer are then removed. In this STI method, the CMP includes contacting a surface of the insulating oxide layer with a surface of a polishing pad, supplying an aqueous solution containing abrasive particles and different first and second passivation agents to an interface between the surface of the polishing pad and the surface of the insulating oxide layer, and rotating the surface of the semiconductor wafer relative to the surface of the polishing pad.
REFERENCES:
patent: 5476606 (1995-12-01), Brancal
Hah Sang-rok
Lee Jae-dong
Lee Jong-won
Yoon Bo-an
Goudreau George
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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