Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2005-09-20
2005-09-20
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
C438S633000, C438S687000, C438S691000, C438S692000
Reexamination Certificate
active
06946397
ABSTRACT:
An oxide polishing process that is part of a CMP process flow is disclosed. After a copper layer is polished at a first polishing station and a diffusion barrier layer is polished at a second polishing station, a key sequence at a third polish station is the application of a first oxide slurry and a first DI water rinse followed by a second oxide slurry and then a second DI water rinse. As a result, defect counts are reduced from several thousand to less than 100. Another important factor is a low down force that enables more efficient particle removal. The improved oxide polishing process has the same throughput as a single oxide polish and a DI water rinse method and may be implemented in any three slurry copper CMP process flow.
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Co-pending U.S. Appl. No. 10/723,236, filed Nov. 26, 2003, same assignee, “An Advanced Process Control Approach for Cu Interconnect Wiring Sheet Resistance Control”.
Co-pending U.S. Appl. No. 10/627,795, filed Jul. 25, 2003, same assignee, “Barrier-Slurry-Free Copper CMP Process”.
Chen Ying-Ho
Chiou Wen-Chih
Chung Chi-Wei
Chung Chia-Che
Hong William
Haynes and Boone LLP
Nguyen Thanh
Taiwan Semiconductor Manufacturing Company , Ltd.
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