Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1998-12-21
2001-03-13
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000
Reexamination Certificate
active
06200875
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method of chemical mechanical polishing and, more particularly, a method of chemical mechanical polishing using an oxide slurry and a polish stop layer to polish both polysilicon and oxide simultaneously in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) devices are widely used in the art. The formation of polysilicon cylindrical capacitors is becoming important. Often, a polysilicon plug is used to form the bottom portion of the cylindrical capacitor. Chemical mechanical polishing (CMP) is routinely used to planarize the polysilicon plugs. However, this demands a polysilicon slurry and may demand a dedicated polisher for polysilicon. It would simplify the process to use an oxide slurry for CMP of the polysilicon plug. Oxide slurry easily removes polysilicon as well. The drawback to this idea is that the oxide slurry easily removes both the polysilicon and the inter-poly oxide (IPO) leading to uncontrollable depth of the polysilicon plug and uncontrollable IPO thickness. It is suggested to employ a polish stop layer before patterning of the polysilicon plug. This would allow polishing of the polysilicon and oxide using an oxide slurry but without polishing away the IPO.
Polish stop layers have been widely used in the art. For example, U.S. Pat. No. 5,759,917 to Grover et al discloses an oxide CMP process using a silicon nitride stop layer to form shallow trench isolation. U.S. Pat. No. 5,229,326 to Dennison et al teaches a poly plug process in which the IPO layer is first subjected to CMP, then polysilicon is deposited and CMP to form poly plugs. This process requires two CMP steps and does not use a stop layer. U.S. Pat. No. 5,700,706 to Juengling teaches a simultaneous CMP of polysilicon and BPSG, but does not use a stop layer.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for controllably simultaneously polishing polysilicon and oxide.
Another object of the present invention is to provide a method for controllably simultaneously polishing polysilicon and oxide using a polish stop layer over the oxide.
Another object of the present invention is to provide a method for controllably simultaneously polishing polysilicon and oxide using a silicon nitride polish stop layer over the oxide.
Yet another object of the present invention is to provide a method for controllably simultaneously polishing polysilicon and oxide using an oxide slurry and a polish stop layer over the oxide.
Yet another object is to provide a method for fabricating a cylindrical capacitor using a polysilicon plug in which the inter-poly oxide and the polysilicon plug can be polished simultaneously and controllably.
A further object is to provide a method for fabricating a cylindrical capacitor using a polysilicon plug in which the inter-poly oxide and the polysilicon plug can be polished with an oxide slurry simultaneously and controllably.
A still further object is to provide a method for fabricating a cylindrical capacitor having a polysilicon plug in which the inter-poly oxide and the polysilicon plug can be polished with an oxide slurry simultaneously and controllably using a polish stop layer over the inter-poly oxide.
In accordance with the objects of this invention, a method for controllably simultaneously polishing polysilicon and oxide using an oxide slurry and a polish stop layer over the oxide is achieved. Semiconductor device structures are provided in and on a semiconductor substrate. An oxide layer is deposited overlying the semiconductor device structures. A silicon nitride layer is deposited overlying the oxide layer as a polish stop layer. A contact opening is etched through the silicon nitride layer and the oxide layer to one of the semiconductor device structures. A polysilicon layer is deposited overlying the silicon nitride layer and within the contact opening. The polysilicon layer is polished until the silicon nitride layer is contacted and then the polysilicon layer, silicon nitride layer, and oxide layer are overpolished in a timed polish to remove the silicon nitride layer and planarize the oxide layer to complete simultaneous planarization of the oxide and polysilicon layers in the fabrication of an integrated circuit device.
REFERENCES:
patent: 5229326 (1993-07-01), Dennison et al.
patent: 5279989 (1994-01-01), Kim
patent: 5318663 (1994-06-01), Buti et al.
patent: 5700706 (1997-12-01), Juengling
patent: 5759917 (1998-06-01), Grover et al.
patent: 6001682 (1999-12-01), Chien
patent: 6008084 (1999-12-01), Sung
patent: 6008085 (1999-12-01), Sung et al.
patent: 6037213 (2000-03-01), Shih et al.
patent: 6060353 (2000-05-01), Koh
patent: 6103569 (2000-08-01), Teo et al.
Wolf et al. “Silicon Processing for the VLSI Era”, vol. 1, p. 194, Lattice Press, 1986.
Chang Chung-Long
Jang Syun-Ming
Ackerman Stephen B.
Chaudhuri Olik
Duy Mai Anh
Pike Rosemary L. S.
Saile George O.
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