Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2002-01-23
2003-12-23
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S633000, C438S691000
Reexamination Certificate
active
06667239
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of chemical mechanical polishing (CMP) in semiconductor fabrication. More particularly, the present invention relates to CMP of copper-oxide damascene structures to increase material removal rate and reduce copper dishing and oxide overpolishing.
BACKGROUND OF THE INVENTION
The continuing advance in ultra-large scale integration (ULSI) of semiconductor devices necessitates design and fabrication of extremely small devices. The existing metallization schemes for interconnects are inadequate for new integrated circuits (ICs). It is projected that for CMOS circuits with gate dimensions less than 0.25 &mgr;m, the RC delay due to metallization layers will account for 50 percent of the total circuit delay. New materials and processes are continuously being sought to replace current Al interconnects to reduce RC delay and energy loss due to heat dissipation. Copper has emerged as the favored interconnect material of the future due to its lower electrical resistivity which is about 30 percent less than that of aluminum (Al). This allows ICs to operate at a higher frequency and lower power. Additionally, as the interconnect dimensions are scaled down, the current density carried by the metal interconnects increases proportionally and might exceed the limit of electromigration. The higher melting point of Cu provides a greater resistance to electromigration which is about 2.5 times greater than Al, thus dramatically increasing the reliability of the ICs.
Despite the inherent advantage of Cu as the interconnect metal however, several challenges are involved in the fabrication of copper lines. Because of lack of volatile copper compounds at low temperature (less than 100° C.), copper etching to form the desired pattern on the top of the inter-level dielectric (ILD) layer is difficult. Thus a new way to pattern Cu lines by damascene scheme followed by CMP has demonstrated a great potential for developments in the interconnect technology.
One problem of the damascene scheme is dishing and overpolishing of the patterns during chemical mechanical polishing.
FIGS. 1A and 1B
schematically show a metal damascene structure before and after chemical mechanical polishing (CMP). In the metal damascene process, the metal interconnects are fabricated by depositing metals onto trenches of etched inter-level dielectric (ILD) layer. Then CMP is employed to remove the excessive metal and form patterned conductive wires in the ILD trenches. In order to remove all the metal coating on the dielectric surface so that the metal interconnects are isolated, the pattern within a die is partially overpolished. Concurrently, the softer interconnect metals (Cu, W) usually wear faster than the diffusion barrier layers (Ta, Ti, or TaN) and the surrounding dielectric material (SiO
2
). Therefore, dishing occurs on the soft metal filled in the trenches. Both overpolishing and dishing degrade the surface planarity and may result in exposure field (die-scale) being partially out of focus in the subsequent lithography process. Moreover, overpolishing and dishing reduce the cross-sectional area of metal interconnects and thus increase the electrical resistance.
Dishing and overpolishing rates may be estimated by Preston equation
ⅆ
h
ⅆ
t
=
k
p
(
x
,
y
)
p
av
φ
(
w
,
A
f
,
t
*
…
)
v
R
The Preston constant k
p
, is a function of position which relates to the physical layout of the oxide and Cu interconnects. It is assumed that the Preston constants for different materials remain the same as those on blanket polishing. The pressure distribution is affected by the actual shape of the dished/overpolished surfaces, which in turn is a function of Cu linewidth w, area fraction A
f
and overpolishing time t*. The pressure distribution can be decoupled as a product of the average pressure on the die area and a geometrical function &phgr; which includes the effects of pattern geometry. In practice, the geometrical function &phgr; is not easy to find even when the surface topography is known. In this case, surface variation due to dishing and overpolishing is comparable to the surface roughness of the pad and the slurry particle size.
In prior art, phenomenological and contact models are proposed to determine the mechanisms of dishing and overpolishing in order to increase the process yield of CMP. The phenomenological model is proposed to relate the polishing rate of arrays of various features to the feature dimension and pattern density. By experimentally determining the correlation between the polishing rate, feature dimensions, and the neighboring feature layout, the surface profile evolution is predicted. One problem of the phenomenological model is that the correlation between the polishing rate and pattern geometry varies with different pattern design, and the tribological mechanisms of planarization are left unanswered in this model. Recently, the effects of pattern geometrical parameters, such as pattern density (i.e., high feature area fraction), pitch, pattern area, and the ratio of perimeter to area, are extensively studied, and the studies show that the pattern density significantly affects the sub-die-scale polishing rate. The influential range of a specific pattern on the neighboring area is characterized by a planarization length measured experimentally. A density-based numerical model is proposed to calculate the surface topography evolution for arbitrary layouts.
Contact models are employed to investigate the mechanisms of planarization. A planar elastic pad is assumed under this model for predicting the pressure distribution on the die surface with various pattern layouts. A generalized relation between pressure distribution and the pad displacement is proposed. Based on this model, the nonuniform polishing rate across different pattern regions is attributed to the nonuniform pressure on the high features. The low features are assumed to stay intact without material being removed until the deformed pat contacts them. However, the contact model may not be applicable to some pattern layouts in metal polishing cases. The pad may be in contact with the low features before the high features reach steady-state profiles. Additionally, the pad may not be conformal to the surfaces of high features as assumed in this model.
Both the phenomenological and the contact models have their limitations in explaining dishing and overpolishing. In Cu polishing, for example, the surface often becomes planar before the Cu layer is polished through. Thus the pressure distribution at the onset of dishing and overpolishing is likely to be much more uniform than that in the planarization stage. Furthermore, when the size of the planarized feature is close to or smaller than the abrasive particle (0.2-0.3 &mgr;m) and the pad surface roughness, the particle distribution and the pad local topography must be taken into account in the calculation of local pressure. An analytical model of this sort is however, difficult to establish. Consequently, the research on dishing and overpolishing has been confined to experimental characterization and parametric studies on pattern parameters such as area fraction, linewidth and pitch. Though a few semi-empirical models have been proposed, the fundamentals of dishing and overpolishing and their relation to pattern geometry and material properties are still not fully understood. Moreover, since most of the experiments are conducted on features of large size, the results and associated problems, such as severe dishing on 100 &mgr;m features, may be inapplicable to current sub-quarter micron circuit design in which the scaling issue must be addressed.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of chemical mechanical polishing of metal damascene structures.
It is another object of the present invention to provide a method of chemical mechanical polishing of metal damascene structures that maximize metal removal rate and m
Lai Jiun-Yu
Oh Hilario L.
Saka Nanaji
ASML US, Inc.
Dorsey & Whitney LLP
Picardat Kevin M.
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