Chemical mechanical polishing method using double polishing...

Details Chemical mechanical polishing method using double polishing... Chemical mechanical polishing method using double polishing...

2000-03-17

2001-06-19

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S424000, C438S427000, C438S692000, C438S959000

Reexamination Certificate

active

06248667

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a chemical mechanical polishing (CMP) method.
2. Description of the Related Art
High performance and highly integrated semiconductor devices such as 256 mega byte and 1 giga byte dynamic random access memories (DRAM) require ultra large scale integration (ULSI). Technologies for forming fine patterns and three-dimensional multi-layer structures are essential to effectively manufacture highly integrated semiconductor devices. Therefore, it is necessary to introduce a new more efficient and precise process to manufacture semiconductor devices. When multi-layered fine wiring is formed by a pattern forming technology, it is essential to planarize an interlayer dielectric (ILD) layer existing under the fine wiring. A partial planarization processing technology is generally used to planarize a layer of a semiconductor device. More recently, a global planarization technology called chemical mechanical polishing (CMP) for planarizing an entire wafer surface has been in use since the mid 1980's. CMP technology improves processing efficiency of semiconductor devices and the quality of the semiconductor devices formed thereby.
CMP technology is applied in semiconductor device manufacturing, i.e., for planarizing an ILD layer, for planarizing metal wiring, and for planarizing a trench structure in an element isolation process. Accordingly, CMP technology improves the depth of focus (DOF) of exposing light in a photolithography process, allows multi-layer wiring to be formed in fine patterns, and improves the step difference between memory cell areas and adjacent peripheral circuit areas in memory devices. Therefore, after CMP technology was introduced to semiconductor device manufacturing, much development was made with respect to element isolation technology to improve the degree of integration, realize fine pattern structure, and to improve global planarization of multi-wiring semiconductor devices. Due to the above-mentioned advantages of CMP technology, research on CMP equipment, articles of consumption for the CMP equipment, and process design using CMP technology, are continuing.
A trench planarization process of an element isolation process is disclosed in U.S. Pat. No. 5,494,857, titled chemical mechanical planarization of shallow trenches in semiconductor substrates, filed on Feb. 27, 1996 and issued to Digital Equipment Corporation (DEC).
FIGS. 1 and 2
are cross-sectional views describing a CMP method according to conventional technology.
Referring to
FIG. 1
, a polishing stopper
53
such as a silicon nitride (SiN) layer is formed on a semiconductor substrate. A trench is formed by etching a predetermined area of the semiconductor substrate
51
in order to form the isolation layer. Then, an oxide layer
55
which can operate as the isolation layer is deposited on the semiconductor substrate
51
covering the entire surface of the semiconductor substrate
51
. The semiconductor substrate
51
is divided into a field area
12
, where a field oxide layer is formed in a relatively wide area, and a pattern area
10
in which a separate element such as a memory cell is formed.
With reference to
FIG. 2
, an isolation layer
55
′ for separating adjacent active areas is formed on the surface of the semiconductor substrate by global planarization in which the CMP process is performed on the surface of the semiconductor substrate
51
on which the oxide layer
55
is stacked. In the CMP process, the polishing stopper layer
53
, which is formed of a SiN layer, prevents the oxide layer
55
from being polished, by which it is possible to achieve global planarization. To planarize the polishing stopper layer made up of a SiN layer or a boron nitride (BN) layer in the CMP process, silica-based slurry is used. In order to planarize the SiN layer or a polysilicon layer in the CMP process, Ceria-based slurry is used.
However, the CMP method has the following problems. First, a dishing phenomenon (D of
FIG. 2
) occurs in which a recessed isolation layer
55
and not a flat isolation layer is formed in the field area
12
. It is considerably difficult to prevent the occurrence of the dishing phenomenon because the dishing phenomenon occurs naturally even though the CMP process uses a slurry having high polishing selectivity.
Second, a thickness variation of the polishing stopper
53
is generated in the pattern area (A of
FIG. 2
) which is adjacent to the field area
12
. The non-uniform thickness of the polishing stopper
53
deteriorates the electrical performance and the reliability of the semiconductor device when the semiconductor device manufacturing processes are completed.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, there is provided a chemical and mechanical polishing (CMP) method using a double polishing stopper, by which it is possible to prevent a dishing phenomenon and the variation of the thickness of a polishing stopper in a CMP process. More specifically, according to a first embodiment of the present invention, a first and second polishing stopper are sequentially stacked, to form a double polishing stopper on a semiconductor substrate. A trench is formed by patterning the first and second polishing stoppers and etching the semiconductor substrate under the first polishing stopper. An isolation layer for covering the semiconductor substrate is stacked on the entire surface of the semiconductor substrate in which the trench was formed. A first CMP process is performed on the isolation layer using the second polishing stopper. The second polishing stopper is removed using the etching selectivity of the second polishing stopper to the first polishing stopper. A second CMP process is performed using the first polishing stopper.
In accordance with another aspect of the present invention, a second polishing stopper and a first polishing stopper are formed of a polysilicon layer and a nitride layer, respectively. The first and second polishing stoppers may be formed of a layer including a polysilicon layer, a silicon nitride (SiN) layer, or a boron nitride (BN) layer. The first and second polishing stoppers are respectively formed to a thickness of between 100 and 10,000 Å.
In accordance with a feature of the present invention, an isolation layer is formed of USG, PSG, BSG, BPSG, and/or an oxide layer using HDP, TEOS, or FOX.
Further, in accordance with another aspect of the present invention, the ratio of the polishing rate of an isolation layer to the polishing rate of a second polishing stopper is larger than 1. The ratio of the etching rate of the second polishing stopper to the etching rate of the isolation layer is larger than 5.
In accordance with still another aspect of the present invention, the ratio of the etching rate of a second polishing stopper to the etching rate of a first polishing stopper is larger than 5. The ratio of the polishing rate of an isolation layer to the polishing rate of the first polishing stopper is larger than 1.
In accordance with another aspect of the present invention, a chemical mechanical polishing (CMP) method using a double polishing stopper is provided. More specifically, a first polishing stopper, an etching stopper, and a second polishing stopper are sequentially stacked on a semiconductor substrate. A trench is formed by patterning the first polishing stopper, the etching stopper, and the second polishing stopper and etching the semiconductor substrate under the first polishing stopper. An isolation layer for covering the semiconductor substrate is stacked on the entire surface of the etched semiconductor substrate. A first CMP process is performed on the isolation layer using the second polishing stopper. The second polishing stopper is removed using the etching stopper. A second CMP process i

Affiliated with

Also associated with

Rating

Chemical mechanical polishing method using double polishing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chemical mechanical polishing method using double polishing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chemical mechanical polishing method using double polishing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2470394