Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-02-14
2003-12-09
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C438S627000, C438S628000, C438S629000, C438S634000
Reexamination Certificate
active
06660629
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a multi-level metal interconnect for a semiconductor device. Particularly, the invention relates to a method of fabricating a copper damascene.
2. Description of Related Art
When an integrated circuit (IC) has gradually increased its integration, with a reduction of a width of metal line, a conventional aluminum interconnect increases its resistance as a result, while a denser distribution of electrical current usually leads to a more serious electro-migration. As the resistance of the metal interconnect increases, the device suffers from an increase in RC time delay and an increase in capacitance between the metal interconnects. Therefore, the operation speed of the device is reduced. The electro-migration causes a short circuit in the aluminum interconnect. Therefore, copper that has a lower resistance and exhibits a lower electro-migration, has become a unique choice for all semiconductor manufacturers. In addition, the copper interconnect can approximately double the operation speed of the device when comparing with the aluminum interconnect.
Since copper itself is not easily etched by a conventional etching gas, the fabrication of the copper interconnect can not be accomplished by the conventional etching method, but is achieved by a damascene technique. The damascene technique involves forming an opening for a metal interconnect, such as a damascene opening in a dielectric layer, followed by filling the damascene opening with metal so as to achieve the metal interconnect technique.
FIGS. 1A through 1C
are schematic diagrams illustrating a conventional fabrication process of the copper damascene.
Referring to
FIG. 1A
, a substrate
100
is provided with devices and conductive lines formed thereon. A dielectric layer
110
is formed on the substrate
100
, followed by forming a damascene opening
120
in the dielectric layer
110
, wherein the damascene opening
120
exposes the devices and conductive lines which serve as electrical connects. A conformal barrier layer
130
and a copper seeding layer
140
are then formed in sequence on the substrate
100
. The damascene opening
120
is a dual damascene opening comprising a via hole and a trench for forming a plug and a conductive line, respectively. The via hole represents a narrow portion of the damascene opening
120
, while the trench represents a wide portion of the damascene opening
120
. The copper seeding layer
140
is formed to improve a quality of the copper layer in the subsequent process.
Referring to
FIG. 1B
, a copper layer
150
is formed on the copper seeding layer
140
, wherein the copper layer
150
is thick enough to fill the damascene opening
120
.
Referring to
FIG. 1C
, a chemical mechanical polishing (CMP) step is performed to remove portions of the copper layer
150
, copper seeding layer
140
, and the barrier layer
130
outside the damascene opening
120
. As a result, a copper damascene
150
a,
such as copper dual damascene is formed, including a copper plug that is represented by a narrow portion of the copper damascene
150
a
and a copper line that is represented by a wide portion of the copper damascene
150
a.
However, the conventional fabrication method for a copper damascene produces a dishing issue for the copper damascene, as shown in FIG.
1
C. As copper is a soft material, a serious dishing occurs on the surface of the copper damascene
150
a,
when the CMP step is performed to form the copper damascene having a large area. For example, in a 0.8-1 micron copper damascene process, a dishing with a size of greater than 0.1 micron can occur on the surface of the copper damascene
150
a.
It has been known that such dishing can reduce a planarity of the substrate. Thus, this negatively affects the lithographic process for each metal interconnect in the subsequent process.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a copper damascene, which method improves a dishing issue encountered in the conventional fabrication method for the copper damascene.
The method of fabricating the copper damascene is applicable to a substrate, which substrate has a dielectric layer formed thereon. The method comprising forming a damascene opening in the dielectric layer, forming a barrier layer which conforms to a profile of the damascene opening over the substrate, and forming a conformal copper seeding layer on the barrier layer. A copper layer is then formed on the copper seeding layer, wherein the copper seeding layer is thick enough so that the damascene opening is filled, followed by forming a conformal protective layer on the copper layer. A first chemical mechanical polishing (CMP) step is performed to remove the protective layer, while a portion of the copper layer outside the damascene opening is removed until the protective layer is completely removed. The first CMP step includes a first polishing rate for the copper layer and a second polishing rate for the protective layer, wherein the first polishing rate is faster than the second polishing rate. A second CMP step is further performed to remove portions of the copper layer, the copper seeding layer, and the barrier layer outside the damascene opening, so as to form a copper damascene. A third polishing rate for the copper layer is provided in the second CMP step, wherein the third polishing rate is slower than the first polishing rate.
As embodied and broadly described herein, the invention provides a fabrication method for the copper damascene. Since the protective layer is conformal to the profile of the damascene opening in the dielectric layer, a portion of the protective layer in the damascene opening is lower than a remaining portion of the protective layer outside thereof. Accordingly, as a polishing step for the portion of protective layer in the damascene opening begins to take place, the polishing step for the remaining portion of the protective layer has long been completed, with a portion of the copper layer thereunder being removed in the first CMP step. Also, the polishing rate for the copper layer is faster than that of the protective layer in the first CMP step, so a portion of the copper layer in the damascene opening is higher than a remaining portion of the copper layer outside thereof after removal of the protective layer. Therefore, the portion of the copper layer in the damascene opening provides a dummy portion to resolve a problem created by a faster polishing rate. As a result, the copper damascene having a planar surface is yielded. Furthermore, the polishing rate for the copper layer is reduced in the second CMP step, so an amount of the copper layer being polished is accurately controlled to prevent a dishing issue due to an over-polishing on the copper damascene.
According to the fabrication method for the copper damascene of the invention, the protective layer having the smaller polishing rate serves as a buffer layer, so as to delay a time for polishing the copper layer in the damascene opening. Therefore, this solves the problem produced by a fast polishing rate, and yields the copper damascene having a planar surface. In addition, the polishing rate for the copper layer is reduced in the second CMP step, so the dishing issue due to the over-polishing on the copper damascene is prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6001730 (1999-12-01), Farkas et al.
patent: 6103625 (2000-08-01), Marcyk et al.
patent: 6150269 (2000-11-01), Roy
patent: 6171957 (2001-01-01), Maekawa
patent: 6258711 (2001-07-01), Laursen
patent: 2002/0016066 (2002-02-01), Birang et al.
Fourson George
J.C. Patents
Maldonado Julio J.
Taiwan Semiconductor Manufacturing Co. Ltd.
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