Chemical/mechanical polishing for ULSI planarization

Details Chemical/mechanical polishing for ULSI planarization Chemical/mechanical polishing for ULSI planarization

1993-09-20

1994-07-26

Powell, William

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156637, 156643, 156645, 156644, 156656, 156657, 437225, H01L 21306, B44C 122, C03C 1500, C23F 100

Patent

active

053324676

ABSTRACT:
A method of planarizing a wafer surface by using a polishing stop with chemical/mechanical polishing is described. A semiconductor wafer, on which there is a rugged surface with broad indentations, is provided. A first layer is formed over the rugged surface. A hard film layer is formed over the first layer. The first layer and the hard film layer are patterned to form polishing stop islands in the broad indentations. A second layer is formed over the rugged surface and the polishing stop islands, to create a top surface for polishing, the top surface and the rugged surface being less hard than the hard film layer. The top surface is polished in a vertical direction to remove portions of the top surface, until the top surface is co-planar with the top of the polishing stop islands. The remainder of the hard film layer is removed to complete the planar surface.

REFERENCES:
patent: 4676867 (1987-06-01), Elkins et al.
patent: 5036015 (1991-06-01), Sandhu et al.
patent: 5081421 (1992-01-01), Miller et al.
patent: 5081796 (1992-01-01), Schultz
patent: 5084071 (1992-01-01), Nenadic et al.
patent: 5084419 (1992-01-01), Sakao
patent: 5094972 (1992-03-01), Pierce et al.
patent: 5246884 (1993-09-01), Jaso et al.
VLSI Technology, published by McGraw-Hill International-Singapore, 1988, pp. 255-257.
"A Planarization Technology Using a Bias-Deposited Dielectric Film and an Etch-Back Process" published in IEEE Transactions on Electron Devices, No. 1988.

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