Chemical mechanical polishing for forming a shallow trench...

Details Chemical mechanical polishing for forming a shallow trench... Chemical mechanical polishing for forming a shallow trench...

1998-07-07

2001-01-02

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S778000, C438S791000

Utility Patent

active

06169012

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87108699, filed Jun. 3, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a chemical mechanical polishing (CMP) applied in forming shallow trench isolation (STI), and more particularly, to a processs of forming a STI structure combining CMP, using a partial reverse active mask.
2. Description of Related Art
CMP is now a technique ideal for appling in global planarization in very large scale integration (VLSI) and even in ultra large scale integration (ULSI). Moreover, CMP is likely to be the only reliable technique as the feature size of the integrated circuit (IC) is highly reduced. Therefore, it is of great interest to develope and improve the CMP technique in order to cut down the cost.
As the IC devices are contineously sized down to a linewith of 0.25 &mgr;m or even 0.18 &mgr;m (deep sub-half micron), using CMP to planarize the wafer surface, especially to planarize the oxide layer on the surface of the shallow trench, becomes even more important. To prevent the dishing effect occuring at the surface of a larger trench during CMP process and to obtain a superior CMP uniformity, a reverse tone active mask was proposed, cooperated with an etching back process.
Typically, the active regions have varied sizes and the shallow trenches between the active regions also have different sizes.
FIGS. 1A
to
1
E are cross sectional veiws showing the process steps for forming shallow trench isolation, using CMP. Referring to
FIG. 1A
, on a substrate
10
, a pad oxide
15
and a silicon nitride layer
16
are deposited successively. By photolithography, the substrate
10
, the pad oxide layer
15
and the silicon nitride layer
16
are anisotropically etched to form shallow trenches
14
a
,
14
b
,
14
c
and define active regions
12
a
,
12
b
,
12
c
,
12
d
. The sizes of the shallow trenches
14
a
,
14
b
,
14
c
are different since the sizes of the active regions
12
a
,
12
b
,
12
c
,
12
d
are varied.
Next, referring to
FIG. 1B
, an oxide layer
18
is deposited by atmosphere pressure chemical vapor deposition (APCVD) on a substrate
10
to fill the interior of the shallow trenches
14
a
,
14
b
,
14
c
. However, due to the step coverage of the oxide layer
18
, the deposited oxide layer
18
has an uneven surface and a rounded shaped. Then, a photoresist layer is coated on the surface of the oxide layer
18
and patterned to form a reverse active mask
20
by photolithography. The reverse active mask
20
covers the shallow trenches
14
a
,
14
b
,
14
c
and is complementary to the active regions
12
a
,
12
b
,
12
c
,
12
d
. However, during the formation of the reverse active mask, misalignment causes the oxide layer
18
to cover more than the shallow trenches
14
a
,
14
b
,
14
c.
Referring to
FIG. 1C
, the oxide layer
18
exposed outside the reverse active mask
20
is etched until the silicon nitride layer
16
is exposed so that only a part of the silicon oxide layer
18
, the silicon oxide layer
18
a
, is formed. After removing the reverse active mask
20
, as shown in
FIG. 1D
, it is obserable that the silicon oxide layer
18
a
remained does not fully cover the shallow trenches
14
a
,
14
b
,
14
c
at one sides of the shallow trenches
14
a
,
14
b
,
14
c
, therefore, forming cavities
22
, but at the other sides over-cover the shallow trenches
14
a
,
14
b
,
14
c
, forming photo-overlape
24
.
Referring to
FIG. 1E
, the portion of the oxide layer
18
a
higher than the shallow trenches
14
a
,
14
b
,
14
c
is polished by CMP until the surface of the silicon nitride layer
16
is exposed. Therefore, the silicon nitride layer
16
and the silicon oxide layer
18
a
are at the same level. The profile of the silicon oxide layer
18
a
formed by APCVD is rather rounded and the APCVD silicon oxide layer
18
a
is hard to be planarized. Moreover, it is obvious that the silicon oxide layer
18
a
does not fully fill the shallow trenches
14
a
,
14
b
,
14
c
but form the concaves
22
. The undesired concaves
22
may cause kink effect and consequent short circuit or leakage current which therefore influence the yield.
As a result, it is important to overcome the problems coming after the formation of the concaves due to the misalignment of the reverse active mask during the process of CMP, especially, while nowadays the linewidth is decreasing.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method of chemical-mechanical polishing for forming a shallow trench isolation. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.


REFERENCES:
patent: 5459096 (1995-10-01), Venkatesan et al.
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5902752 (1999-05-01), Sun et al.
patent: 5911110 (1999-06-01), Yu
patent: 5923993 (1999-07-01), Sahota
patent: 5958795 (1999-09-01), Chen et al.
patent: 6013558 (2000-01-01), Harvey et al.

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