Chemical mechanical polishing apparatus and methods with...

Details Chemical mechanical polishing apparatus and methods with... Chemical mechanical polishing apparatus and methods with...

2000-12-22

2003-10-28

Picard, Leo (Department: 2125)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S121000

Reexamination Certificate

active

06640155

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to chemical mechanical polishing (CMP) systems and techniques for improving the performance and effectiveness of CMP operations. Specifically, the present invention relates to controlling the forces applied to carrier heads for wafers and pad conditioning pucks, and to retaining rings on such carrier heads, to separately apply programmably variable respective pressures on respective ones of the wafers, pad conditioning pucks, and retaining rings with or independently of changes in the value of the contact areas on which the forces are applied, to foster repeatable CMP operations on successively polished wafers.
BACKGROUND OF THE INVENTION
DESCRIPTION OF THE RELATED ART
In the fabrication of semiconductor devices, there is a need to perform CMP operations, including polishing, buffing and wafer cleaning. For example, a typical semiconductor wafer may be made from silicon and may be a disk that is 200 mm or 300 mm in diameter. For ease of description, the term “wafer” is used below to describe and include such semiconductor wafers and other planar structures, or substrates, that are used to support electrical or electronic circuits.
Typically, integrated circuit devices are in the form of multi-level structures fabricated on such wafers. At the wafer level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. Patterned conductive layers are insulated from other conductive layers by dielectric materials. As more metallization levels and associated dielectric layers are formed, the need to planarize the dielectric material increases. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove excess metallization.
In a typical CMP system, a wafer is mounted on a carrier with a surface of the wafer exposed. The carrier and the wafer rotate in a direction of rotation. The CMP process may be achieved, for example, when the exposed surface of the rotating wafer and a polishing pad are urged toward each other by a force, and when the exposed surface and the polishing pad move or rotate in a polishing pad direction. Some CMP processes require that a significant force be used at the time the rotating wafer is being polished by the polishing pad.
Several problems may be encountered while using a typical CMP system. One recurring problem is called “edge-effect,” which is caused when the CMP system polishes an edge of the wafer at a different rate than other regions of the wafer. The edge-effect is characterized by a non-uniform profile on the exposed surface of the wafer. The problems associated with edge-effect can be divided to two distinct categories. The first category relates to the so-called “pad rebound effect” resulting from the initial contact of the polishing pad with the edge of the wafer. When the polishing pad initially contacts the edge of the wafer, the pad rebounds (or bounces off) the edge, such that the pad may assume a wave-like shape. The wave-like shape may produce non-uniform profiles on the exposed surface of the wafer.
The second category is the “burn-off” effect. The burn-off effect occurs when a sharper edge of the wafer is excessively polished as it makes contact with the surface of the polishing pad. This happens because a considerable amount of pressure is exerted on the edge of the wafer as a result of the surface of the pad applying the force on a very small contact area of the exposed surface of the wafer (defined as the edge contact zone). As a consequence of the burn-off effect, the edges of the resulting polished wafers exhibit a bum ring that renders the edge region unusable for fabricating silicon devices.
Another shortcoming of conventional CMP systems is an inability to polish the surface of the wafer along a desired finishing layer profile. Ordinarily, the exposed surface of a wafer that has undergone some fabrication tends to be of a different thickness in the center region and varies in thickness out to the edge. In a typical conventional CMP system, the pad surface covers the entire exposed surface of the wafer. Such pad surface is designed to apply a force on a so-called “finishing layer” portion of the exposed surface of the wafer. As a result, all the regions of the finishing layer are polished until the finishing layer is substantially flat. Thus, the surface of the pad polishes the finishing layer irrespective of the wavy profile of the finishing layer, thereby causing the thickness of the finishing layer to be non-uniform. Some circuit fabrication applications require that a certain thickness of material be maintained in order to build a working device. For instance, if the finishing layer were a dielectric layer, a certain thickness would be needed in order to define metal lines and conductive vias therein.
These problems of prior CMP operations, and an unsolved need in the CMP art for a CMP system that enables precision and controlled polishing of specifically targeted wafer surface regions, while substantially eliminating damaging edge-effects, pad rebound effects, and edge burn-off effects, are discussed in the First Parent Application identified above.
In such First Parent Application, a CMP system follows the topography of layer surfaces of the exposed surface of the wafer so as to create a CMP-processed layer surface which has a uniform thickness throughout. Such CMP system implements a rotating carrier in a subaperture polishing configuration, eliminating the above-mentioned drawbacks, edge-effects, pad rebound effects, and edge burn-off effects. For example, one embodiment of such CMP system includes a preparation head, such as a polishing head, designed to be applied to a portion of the wafer, wherein the portion is less than an entire portion of the surface of the wafer. Although such CMP system avoids the above-described edge-effects, pad rebound effects, and edge burn-off effects, the application of such preparation head in this manner applies a force to the exposed surface of the wafer and to the carrier at a location that is eccentric with respect to an initial orientation of the wafer and the carrier. The initial orientation includes an initial orientation of central axes of the wafer and of the carrier (which are coaxial and positioned substantially vertically). The initial orientation also includes an initial orientation of the exposed surface of the wafer (which is positioned at an initial angle of ninety degrees with respect to the initial substantially vertical orientation of the central axes of the wafer and the carrier). The term “substantially vertical” means true vertical, and includes true vertical plus or minus normal mechanical tolerances from true vertical, such as those tolerances typical in bearings used in spindles and other supports for such carriers.
As may be understood from the above discussion of the edge-effects, pad rebound effects, and edge burn-off effects, it would be undesirable for such eccentric force to cause the central axes of the wafer and the carrier to depart from the initial orientation and to tilt, or assume a tilted orientation. Such tilting or tilted orientation would occur when such central axes of the wafer and/or the carrier depart from true vertical more than the above-described normal mechanical tolerances from true vertical, e.g., by a number of degrees. Such initial orientation of the central axes of the wafer and the wafer carrier is the orientation that must be maintained during polishing under the action of such eccentric force to achieve the desired planarization of the exposed surface of the wafer. In other words, tilting allowed by gimbals must be avoided if the desired planarization of the exposed surface

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