Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-12-20
2003-06-10
Hiteshew, Felisa (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S691000, C438S692000, C438S693000
Reexamination Certificate
active
06576551
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming planarized layers within microelectronic fabrications. More particularly, the present invention relates to chemical mechanical polish (CMP) planarizing methods for forming planarized layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly important within the art of microelectronic fabrication to form patterned microelectronic conductor layers within microelectronic fabrications with enhanced levels of uniformity, and in particular surface planarity uniformity. Such enhanced levels of uniformity, including surface planarity uniformity, provide microelectronic fabrications wherein resistance-capacitance delay times may be optimally minimized, since: (1) patterned microelectronic conductor layers of uniform dimension provide patterned microelectronic conductor layers of predictable current carrying capacity, while; (2) patterned microelectronic conductor layers of uniform surface planarity provide patterned microelectronic conductor layers to which low contact resistance connections to adjoining patterned microelectronic conductor layers may be made within microelectronic fabrications. To the end of providing within microelectronic fabrications patterned microelectronic conductor layers with enhanced uniformity, and in particular with enhanced surface planarity uniformity, it has become common in the art of microelectronic fabrication to fabricated patterned microelectronic conductor layers, including but not limited to patterned microelectronic conductor contact layers and patterned microelectronic conductor interconnect layers, while employing chemical mechanical polish (CMP) planarizing damascene methods.
Similarly, while chemical mechanical polish (CMP) planarizing damascene methods are thus desirable within the art of microelectronic fabrication for forming with enhanced uniformity patterned microelectronic conductor layers within microelectronic fabrications, chemical mechanical polish (CMP) planarizing damascene methods are nonetheless also not entirely without problems when employed in the art of microelectronic fabrication for forming patterned microelectronic conductor layers within microelectronic fabrications. In that regard, it is known in the art of microelectronic fabrication that chemical mechanical polish (CMP) planarizing methods when employed for forming chemical mechanical polish (CMP) planarized patterned microelectronic conductor layers within microelectronic fabrications often provide the chemical mechanical polish (CMP) planarized patterned microelectronic conductor layers with non-optimally planarized dished surfaces to which it is often difficult to reliably connect adjoining patterned microelectronic conductor layers within microelectronic fabrications.
It is thus towards the goal of forming within the art of microelectronic fabrication chemical mechanical polish (CMP) planarized patterned microelectronic conductor layers, as well as other chemical mechanical polish (CMP) planarized microelectronic structures, with enhanced surface planarity uniformity, that the present invention is both more specifically and more generally directed.
Various chemical mechanical polish (CMP) planarizing methods and chemical mechanical polish (CMP) planarizing materials have been disclosed within the art of microelectronic fabrication for forming chemical mechanical polish (CMP) planarized microelectronic layers and chemical mechanical polish (CMP) planarized microelectronic structures with desirable properties within microelectronic fabrications.
For example, Krishnan et al., in U.S. Pat. No. 5,451,551, discloses a chemical mechanical polish (CMP) planarizing method for forming within a microelectronic fabrication a patterned microelectronic conductor layer fully encapsulated within a barrier layer, a surface of which barrier layer is formed planar with a planarized dielectric layer within which is formed the patterned conductor layer fully encapsulated within the barrier layer. The chemical mechanical polish (CMP) planarizing method realizes the foregoing objects by chemical mechanical polish planarizing upon a conformal lower barrier layer formed within a recess within the planarized dielectric layer a chemical mechanical polish (CMP) planarized conductor layer of height less than a remaining depth of the recess, prior to forming and chemical mechanical polish (CMP) planarizing upon the chemical mechanical polish (CMP) planarized conductor layer a conformal upper capping barrier layer contiguous with the conformal lower barrier layer and planar with the planarized dielectric layer.
In addition, Chen et al., in U.S. Pat. No. 5,858,869, discloses a chemical mechanical polish (CMP) planarizing method for forming within a microelectronic fabrication a sandwich composite planarizing dielectric construction which passivates a patterned conductor layer within the microelectronic fabrication, to provide with enhanced process latitude the microelectronic fabrication with a reduced capacitive delay. The chemical mechanical polish (CMP) planarizing method realizes the foregoing objects by employing when forming the sandwich composite planarizing dielectric layer construction a blanket dielectric liner layer formed of an anisotropic plasma oxide formed to a greater thickness upon upper horizontal surfaces of the patterned microelectronic conductor layer within the microelectronic fabrication than upon lower lying sidewall surfaces of the patterned microelectronic conductor layer within the microelectronic fabrication.
Further, Boeck et al., in U.S. Pat. No. 5,880,018, discloses a chemical mechanical polish (CMP) planarizing method for forming within a microelectronic fabrication a series of low dielectric constant inter-level dielectric (ILD) layers formed interposed between the patterns of a patterned microelectronic conductor layer formed within the microelectronic fabrication. The chemical mechanical polish (CMP) planarizing method employs a series of sacrificial dielectric layers which after being employed as a series of chemical mechanical polish (CMP) stop layers for forming the series of patterns within the patterned microelectronic conductor layer within the microelectronic fabrication incident to chemical mechanical polish (CMP) planarizing a blanket microelectronic conductor layer within the microelectronic fabrication is stripped from the microelectronic fabrication to thus provide the series of patterns within the patterned microelectronic conductor layer within the microelectronic fabrication which in turn serve as a series of chemical mechanical polish (CMP) stop layers when forming the series of low dielectric constant inter-level dielectric (ILD) layers formed interposed between the patterns of the patterned microelectronic conductor layer within the microelectronic fabrication incident to chemical mechanical polish (CMP) planarizing a blanket low dielectric constant inter-level dielectric (ILD) layer within the microelectronic fabrication.
Finally, Watts et al., in U.S. Pat. No. 5,897,375, discloses a chemical mechanical polish (CMP) slurry composition for forming within improved properties and process control within a microelectronic fabrication a chemical mechanical polish (CMP) planarized patterned copper containing conductor layer within the microelectronic fabrication. The chemical mechanical polish (CMP) slurry composition comprises an aqueous or alcohol solvent having contained therein: (1) an oxidizing agent such as hydrogen peroxide; (2) a citrate salt; (3) an abrasive powder; and (4) an optional triazole compound.
Desirable in the art of microelectronic fabricati
Chang Weng
Liu Chung-Shi
Ackerman Stephen B.
Hiteshew Felisa
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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