Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-05-29
2001-08-07
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000, C438S692000, C438S699000
Reexamination Certificate
active
06271123
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates to semiconductor manufacture and more particularly to an improved method of chemical mechanical polishing and for forming planarized dielectric layers.
2) Description of the Prior Art
One technique that is used in semiconductor manufacture for planarizing dielectric layers is chemical mechanical polishing (CMP). Chemical-mechanical polishing involves holding and rotating a semiconductor wafer against a wetted polishing platen under controlled chemical, pressure and temperature conditions. Typically an aqueous colloidal silica solution is used as the abrasive fluid. The polishing mechanism is a combination of mechanical action and the chemical reaction of the material being polished with the aqueous solution. As circuit densities increase, chemical mechanical polishing has become one of the most viable techniques for planarization particularly for interlevel dielectric layers. In view of this, improved methods of chemical mechanical polishing are being increasingly sought. One aspect of chemical mechanical polishing in need of improvement is the speed and throughput of the process for semiconductor manufacture. In general, CMP is a relatively slow and time consuming process. During the polishing process semiconductor wafers must be individually loaded into a carrier, polished and then unloaded from the carrier. The polishing step in particular is very time consuming and may require several minutes.
Recently, different techniques have been used in the art for increasing the speed and throughput of the CMP process. As an example, more aggressive aqueous solutions have been developed to increase the speed of the polishing step. Higher carrier downforces and higher rpms for the polishing platen are also sometimes used. Although these techniques are somewhat successful, they may adversely effect the polishing process and the uniformity of the polished surface. Endpoint detection, for instance, is more difficult to control when aggressive solutions and higher carrier downforces are employed. In addition, the polishing process may not proceed uniformly across the surface of the wafer. The hardness or composition of a dielectric layer (or polishing platen) may vary in certain areas. This in turn may cause a dielectric layer to polish faster or slower in some areas effecting its global planarity. This problem may be compounded by aggressive solutions, higher carrier downforces and increased rpms.
In view of these and other problems of prior art CMP processes, there is a need in the art for improved methods of CMP. In addition, there is a need in the art for improved methods of forming and planarizing dielectric layers.
The applicants have found problems in their previous CMP planarization process for ILD layers. This process is not prior art, but an explanation of a problem that the invention solves. As shown in
FIG. 1
, an inter level dielectric (ILD) layer
121
is formed over polysilicon layers
22
A
22
B
22
C over a substrate
10
. The substrate has a high cell area
14
and a lower periphery area
16
. The applicant's inter level dielectric (ILD) layer
121
was formed of three layers: a lower PE-TEOS layer
121
A, a middle thin BTTEOS layer
121
B and a thick PE-TEOS layer
121
C. A stop layer
124
composed of SiN was formed over this ILD layer
121
.
Next, the stop layer
124
and the ILD layer
121
are chemical-mechanical polished as shown in figure
1
A. The ideal CMP result
132
(top surface of IDL layer
121
after CMP) is shown as line
132
. However, when the SiN layer
124
and the IDL layer
121
were chemical-mechanical polished, the actual resulting surface is shown as dotted line
130
. The real surface
130
of the IDL layer
121
after CMP is caused by {circumflex over (
1
)}polish pad dishing and {circumflex over (
2
)}wafer non-uniformity.
Due to the great difference in step height from cell
14
to periphery circuits
16
, the oxide polishing of IPO and ILD layers
121
in embedded DRAM or SRAM suffers poor within-cell and cell-to-periphery planarity. (See dotted line
132
). To resolve this issue, PE-SIN cap layer
124
on ILD
121
(for example, PE-TEOS/BP 03-TEOS )PE-TEOS
121
A,
121
B,
121
C) has been proven viable to improve the global planarity. However, the use of PE-TEOS in ILD or IPO has been found to induce device degradation. The PE-TEOS layer
121
causes excess moisture that results in device degradation. Furthermore, BPSG or BP 03-TEOS is highly preferred as the polishing layer. Moreover, the residual PE-SIN stop layer
124
is unwanted and requires additional wet etch step to remove it completely. Compared with BPSG, the SiN stop layer
124
has much lower polish rate and may not be able to achieve good planarity. Therefore, a stop layer that is compatible with BPSG and can be left after CMP is desired.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,169,491 (Doan) teaches forming a forming a BPSG layer over the USG layer and (
3
) CMP the BPSG layer. U.S. Pat. No. 5,449,314 Meikle et al.) shows a method of CMP planarization where a dielectric layer has a dopant concentration that decreases with depth. (See col. 3, lines 35 to 40). U.S. Pat. No. 5,356,513 (Burke) shows a method of forming alternating soft/hard/soft planarization layers. U.S. Pat. No. 5,314,843 (Yu et al.) shows a method of forming dielectric layerover a substrate and doping specific (high) areas of the dielectric layer to make the CMP rate higher in the doped areas. The areas are doped using a masking process. U.S. Pat. No. 5,332,467 (Sune) shows a CMP method that forms hard polish stops over an oxide layer. U.S. Pat. No. 5,560,802 (Chisholm) shows another CMP method using silicon oxide stop and doped upper layers.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved method of chemical-mechanical polish (CMP) and an improved method of forming and planarizing dielectric layers using chemical-mechanical polish (CMP).
It is a further object of the present invention to provide an method of planarizing a BPSG layer
30
using an overlying Undoped Silicate Glass (USG) cap layer
40
.
It is a further object of the present invention to provide an improved method of CMP that is suitable for large scale semiconductor manufacture and in which increased process speeds and throughput are obtained without sacrificing global planarity.
It is an object of the invention to minimize the amount of PE-TEOS layer remaining after the chemical-mechanical polishing thereby reducing device degradation.
The invention is at least a two layer structure comprising a thick BGSG layer
30
and a thin USG cap layer
40
. The cap layer
40
can remain on the BPSG layer
30
after the CMP process. A key point of the invention is that the top surface of the cap layer
40
in the cell area
14
is higher than the top surface of the BPSG layer
30
in the periphery area
16
(see
FIG. 2
element
35
).
Accordingly, the invention provides a method of planarizing a BPSG layer
30
using a thin USG cap layer
40
; comprising the steps of:
(a) See FIG.
2
—providing a semiconductor structure
18
over a substrate
10
; the semiconductor structure
18
having at least a cell area
14
and a periphery area
16
; the top surface of the semiconductor structure
18
in the cell area
14
being higher than in the periphery area
16
;
(b) forming a first silicon oxide layer
20
using a PE-TEOS process over the semiconductor structure
18
;
(c) forming a BPSG layer
30
on the first silicon oxide layer; the BPSG layer
30
over the periphery area
16
having a first thickness;
(c-1) the BPSG layer
30
has the first thickness in a range of between about 3000 and 15,000 Å;
(d) forming a cap layer
40
compos
Chang Chung-Long
Jang Syun-Ming
Ackerman Stephen B.
Goodwin David
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
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