Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Patent
1998-10-23
2000-07-18
Utech, Benjamin L.
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
438693, 438697, 438710, H01L 21302
Patent
active
060907142
ABSTRACT:
A method for forming a planarized trench fill layer within a trench within a substrate. There is first provided a substrate having a trench formed therein. There is then formed over the substrate and at least partially filling the trench a first trench fill layer formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. There is then formed upon the first trench fill layer a second trench fill layer formed employing a subatmospheric pressure thermal chemical vapor deposition (SACVD) method employing ozone as an oxidant source material and tetraethylorthosilicate (TEOS) as a silicon source material. Finally, there is then planarized by employing a chemical mechanical polish (CMP) planarizing method the second trench fill layer and the first trench fill layer to form a patterned planarized trench fill layer within the trench. When employing the method, the first trench fill layer is formed to a first thickness and the second trench fill layer is formed to a second thickness, where the first thickness and the second thickness are chosen such that there is attenuated erosion of the substrate when forming the patterned planarized trench fill layer within the trench while employing the chemical mechanical polish (CMP) planarizing method. The method is particularly useful for forming patterned planarized trench fill dielectric layers within isolation trenches within semiconductor substrates employed within semiconductor integrated circuit microelectronics fabrications.
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Fu Chu-Yun
Jang Syun-Ming
Ackerman Stephen B.
Brown Charlotte A.
Saile George O.
Szecsy Alek P.
Taiwan Semiconductor Manufacturing Company
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