Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2000-09-29
2002-12-03
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S462000, C438S626000, C438S631000, C438S975000, C438S692000, C257S797000
Reexamination Certificate
active
06489216
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to chemical mechanical polish (CMP) planarizing methods employed for forming chemical mechanical polish (CMP) planarized microelectronic layers within microelectronic fabrications. More particularly, the present invention relates to topographic mark preservation methods employed in conjunction with chemical mechanical polish (CMP) planarizing methods employed for forming chemical mechanical polish (CMP) planarized microelectronic layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly important within the art of microelectronic fabrication to form within the art of microelectronic fabrication microelectronic fabrications having formed therein planarized microelectronic layers. Planarized microelectronic layers are desirable in the art of microelectronic fabrication when fabricating microelectronic fabrications insofar as planarized microelectronic layers within microelectronic fabrications provide microelectronic fabrications within which there may more readily be formed with enhanced functionality and enhanced reliability additional microelectronic layers and additional microelectronic structures within the microelectronic fabrications.
While planarized microelectronic layers are thus clearly desirable in the art of microelectronic fabrication, planarized microelectronic layers are nonetheless not formed entirely without problems in the art of microelectronic fabrication.
In that regard, when forming a planarized microelectronic layer within a microelectronic fabrication by planarizing a non-planarized microelectronic layer within the microelectronic fabrication, particularly when planarizing the non-planarized microelectronic layer while employing a chemical mechanical polish (CMP) planarizing method, there is often obliterated or compromised within a microelectronic substrate over which is formed the planarized microelectronic layer while employing the chemical mechanical polish (CMP) planarizing method a topographic mark, such as but not limited to a topographic alignment mark or a topographic identification mark. As is understood by a person skilled in the art, such a topographic alignment mark or a topographic identification mark is typically employed for either aligning or identifying the microelectronic substrate within which is formed the topographic alignment mark or the topographic identification mark. Such obliteration or comprise of the topographic mark, whether a topographic alignment mark or a topographic identification mark, is undesirable in the art of microelectronic fabrication since subsequent alignment or identification of the microelectronic substrate is thus negatively affected when further fabricating the microelectronic fabrication.
It is thus towards the goal of providing a chemical mechanical polish (CMP) planarizing method for forming within a microelectronic fabrication and over a microelectronic substrate having a topographic mark formed therein a chemical mechanical polish (CMP) planarized microelectronic layer while preserving the integrity of the topographic mark formed within the microelectronic substrate over which is formed the chemical mechanical polish (CMP) planarized microelectronic layer that the present invention is directed.
Various methods, materials and apparatus have been disclosed in the art of microelectronic fabrication for preserving the integrity of a topographic mark formed within a microelectronic substrate employed within a microelectronic fabrication when forming over the microelectronic substrate or processing over the microelectronic substrate a microelectronic layer employed within the microelectronic fabrication.
For example, Ramaswami et al., in U.S. Pat. No. 5,456,756, discloses: (1) a microelectronic substrate clamp; (2) a microelectronic conductor metal layer deposition apparatus which employs the microelectronic substrate clamp; and (3) a method for forming over a microelectronic substrate having a topographic mark formed therein a microelectronic conductor metal layer, wherein there is preserved the integrity of the topographic mark formed within the microelectronic substrate when forming over the microelectronic substrate the microelectronic conductor metal layer while employing the method which employs the microelectronic conductor metal layer deposition apparatus which in turn employs the microelectronic substrate clamp. To realize the foregoing object, the microelectronic substrate clamp employs a tab within an interior periphery of the microelectronic substrate clamp, wherein the tab is located in a position such as to occlude deposition of the microelectronic conductor metal layer over a portion of the microelectronic substrate having the topographic mark formed therein when forming while employing the microelectronic substrate clamp, the microelectronic conductor metal layer deposition apparatus and the method the microelectronic conductor metal layer upon the microelectronic substrate when clamped within the microelectronic substrate clamp.
In addition, Wu et al., in U.S. Pat. No. 5,801,090, discloses a method for preserving the integrity of an alignment mark formed within a semiconductor substrate employed within a semiconductor integrated circuit microelectronic fabrication when chemical mechanical polish (CMP) planarizing over the semiconductor substrate employed within the semiconductor integrated circuit microelectronic fabrication at the location of the alignment mark an intermetal dielectric (IMD) layer formed over the semiconductor substrate employed within the semiconductor integrated circuit microelectronic fabrication. In order to realize the foregoing object, the method employs a selective etching of the intermetal dielectric (IMD) layer at the location of the alignment mark both before chemical mechanical polish (CMP) planarizing the intermetal dielectric (IMD) layer and after chemical mechanical polish (CMP) planarizing the intermetal dielectric (IMD) layer.
Finally, Nguyen et al., in U.S. Pat. No. 6,057,206, discloses a method which may be employed for preserving the integrity of an alignment mark formed within a microelectronic substrate employed within a microelectronic fabrication when chemical mechanical polish (CMP) planarizing a microelectronic layer formed over the microelectronic substrate and covering the alignment mark. To realize the foregoing object, the method may employ with respect to a circular microelectronic substrate an annular photoexposed patterned negative photoresist layer formed at a periphery of the circular microelectronic substrate and covering the alignment mark, where the annular photoexposed patterned negative photoresist layer is formed absent a conventional masking method while employing an edge bead photoresist removal tool intended for removing from over the circular substrate an annular edge bead formed of a positive photoresist material.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed to preserve the integrity of a topographic mark formed within a microelectronic substrate employed within a microelectronic fabrication when chemical mechanical polish (CMP) planarizing a microelectronic layer formed over the microelectronic substrate employed within the microelectronic fabrication at the location of the topographic mark.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a chemical mechanical polish (CMP) planarizing method for forming within a microelectronic fabrication a chemical mechanical polish (CMP) planarized microelec
Chen Dian-Hau
Shiu Ruei-Je
Guerrero Maria
Jr. Carl Whitehead
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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