Checksum writing method and checksum checking apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S807000

Reexamination Certificate

active

07350135

ABSTRACT:
A more convenient checksum writing method and checksum checking apparatus. The method includes: calculating a first checksum by reading values from the memory and summing the read values; calculating a first mode checksum by subtracting values written in a predetermined area of the memory from the first checksum; initializing a second checksum to be zero if the first mode checksum does not meet a predetermined condition; calculating a second mode checksum by inverting the second checksum and adding the inverted second checksum to the first mode checksum; and writing the inverted second checksum value in the predetermined area of the memory, if the second mode checksum is equal to the second checksum.

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patent: 62-1043 (1987-01-01), None
Saxena et al., Analysis of Checksums, Extended-Precision Checksums and Cyclic Redundancy Checks, Jul. 1990, IEEE, vol. 39., pp. 969-975.

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