Checkpointing with a write back controller

Details Checkpointing with a write back controller Checkpointing with a write back controller

2006-08-01

2006-08-01

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S015000, C714S016000, C714S018000, C714S020000, C711S143000

Reexamination Certificate

active

07085955

ABSTRACT:
A checkpointing method and system that utilize a write back controller. The system can include a first controller for implementing a first function, wherein the first function comprises part of a checkpoint operation and wherein the checkpoint operation comprises a series of contiguous checkpoint cycles. The system can also include a second controller, the second controller for implementing a second function, wherein the second function comprises a write back operation from a first memory location to a second memory location and wherein the write back operation occurs before a checkpoint cycle ends. Information already at the second memory location can be selectively written back to a third memory location.

REFERENCES:
patent: 3736566 (1973-05-01), Anderson et al.
patent: 5745672 (1998-04-01), Stiffler
patent: 5933593 (1999-08-01), Arun et al.
patent: 6079030 (2000-06-01), Masubuchi
patent: 6779087 (2004-08-01), Saulsbury et al.
patent: 6810489 (2004-10-01), Zhang et al.

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