Checkpoint acquisition accelerating apparatus

Details Checkpoint acquisition accelerating apparatus Checkpoint acquisition accelerating apparatus

1997-08-27

2000-07-11

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711146, 714 19, G06F 1216

Patent

active

060887737

ABSTRACT:
A novel checkpoint acquisition accelerating apparatus is disclosed. When data are updated on a cache memory, a before-image acquiring section acquires the update address and the previous data and stores them in a before-image storing section. A cache flush executing section issues to a system bus a bus command requesting the contents of the updated cache block to be written-back to a main memory using all the addresses stored in the before-image storing section. A main memory restoring section, on the other hand, issues bus command requesting all the previous data stored in the before-image storing section to be updated and written in the main memory on last-in first-out basis. As a result, a checkpoint acquisition accelerating apparatus is realized which is capable of easily realizing the checkpoint and recovery function in a computer including at least a standard uniprocessor.

REFERENCES:
patent: 4740969 (1988-04-01), Fremont
patent: 5745730 (1998-04-01), Nozue et al.
Relevant portion of Office Action of Application No. 97 115 030.5 dated Jun. 4, 1999.

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