Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-05
2010-06-22
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07743351
ABSTRACT:
The invention provides a system and a method for verifying the robustness of a model of a physical system, the method comprising the following steps: defining a first model of the physical system comprising a set of components and at least one input interface for inserting input values, said first model being defined in a formal language describing the behavior and the function of each of said components; defining in the formal language a determined property that must be satisfied by the model of the physical system; defining in the formal language a second model corresponding to the first model and enriched by a fault injection mechanism; and using formal proof means to search automatically for a combination of injected faults and/or input values that causes said determined property to fail.
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Bregaint Christian
Croix Marie Marc
Granier Hugues
Tonnelier Philippe
Chiang Jack
Hispano Suiza
Memula Suresh
Rothwell, Figg Ernst & Manbeck, PC
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