Checking layout accuracy in integrated circuit designs

Details Checking layout accuracy in integrated circuit designs Checking layout accuracy in integrated circuit designs

2005-09-13

2005-09-13

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06944839

ABSTRACT:
A method for checking layout accuracy in an integrated circuit design includes creating a schematic, adding a line width marker to selected lines having a width greater than an absolute minimum width, and assigning a line width to each line width marker. A layout is created and is checked versus the schematic. A design is extracted from the layout. The design has a design line width corresponding to each line having a line width marker. The design line width is checked versus the marker line width for each line having a line width marker.

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