Checking for valid slice packing in a programmable device

Details Checking for valid slice packing in a programmable device Checking for valid slice packing in a programmable device

2007-04-16

2010-11-09

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07831943

ABSTRACT:
A method of determining validity of slice packing for a programmable device can include identifying a slice topology for a slice, identifying a circuit fragment assigned to the slice, and generating a set of Boolean equations describing conditions for mapping the circuit fragment to the slice according to the slice topology. The method further can include determining whether a solution to the set of Boolean equations exists and indicating whether the slice is validly packed according to whether a solution for the set of Boolean equations is determined.

REFERENCES:
patent: 7028281 (2006-04-01), Agrawal et al.
R. G. Wood and R. A. Rutenbar, “FPGA routing and routability estimation via Boolean satisfiability,” IEEE Trans. VLSI Syst., vol. 16, pp. 222-231, Jun. 1998.

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