Checkerboard parity techniques for a multi-pumped bus

Details Checkerboard parity techniques for a multi-pumped bus Checkerboard parity techniques for a multi-pumped bus

2001-02-14

2004-05-25

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C710S105000

Reexamination Certificate

active

06742160

ABSTRACT:

BACKGROUND
1. Field
This disclosure generally relates to parity or error correction techniques for a multi-pumped bus architecture and protocol.
2. Description of Related Art
Parity techniques have long been used to improve the reliability of signal transfer between bus agents. Bus agents such as processor have traditionally transmitted parity or error correction bits for data elements at the same rate as data elements and/or at the same time as these data elements. For example, some Pentium® processors such as the Pentium Pro® processor, Pentium® II processor, and the Pentium® III processor (hereafter “P6 bus protocol processors”) from Intel Corporation may be configured to transfer data error correction signals using such prior art techniques.
Various details of the bus protocols for the P6 bus protocol processors are found in the Pentium Pro® processor, Pentium® II processor, and the Pentium® III processor Family Developer's Manuals. For example, the P6 bus protocol is described in the Pentium® II Processor Developer's Manual (see, e.g., Chapter 3), October, 1997, Intel document number 243502-001, available from Intel Corporation of Santa Clara, Calif. Some P6 bus protocol processors transmit data error correction signals and address parity signals using a common clock protocol at the same frequency as data signals are transmitted. Such a technique allows data parity to be computed and transmitted with each set of data signals.
Other processors have altered the data transfer protocol by increasing the data transfer rate using a double-pumped, source synchronous protocol. See, for example, PCT publication WO 99/36858. Such processors may also transfer error correction information in a double pumped manner. Using double pumped techniques to also transmit error correction information allows full correction information to be transmitted with each data transfer, but also requires another set of high speed (double pumped) signals to transmit the parity or error correction information and requires parity or error correction generation and checking circuitry that can operate sufficiently fast to support double-pumped transmission of parity information.


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