Checkerboard buffer

Details Checkerboard buffer Checkerboard buffer

2001-07-17

2004-12-14

Chauhan, Ulka J. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Plural storage devices

C345S545000, C345S533000, C345S539000, C345S564000, C345S571000

Reexamination Certificate

active

06831651

ABSTRACT:

BACKGROUND
The present invention is related to video data storage. More particularly, the present invention is related to video display systems and frame buffers. Several related technologies are discussed below (in labeled sections for clarity).
1. Raster-Scan Displays
A common type of graphics monitor is a conventional raster-scan display using a cathode ray tube (“CRT”). As is well known, in a typical CRT, an electron beam strikes phosphor on the inner surface of the screen producing light visible on the outer surface of the screen. By controlling the electron beam different locations of the screen can be struck, creating a pattern and hence a video image. In a typical CRT raster-scan display, the screen area is divided into a grid of pixels (or picture elements). The electron beam sweeps from left to right across the screen, one row at a time from top to bottom, progressively drawing each pixel on the screen. Each row of pixels is commonly referred to as a scan line. In this type of conventional display, the scan lines are horizontal. The number of pixels in a single scan line is referred to as the width. One complete pass over the screen and the pixels in that pass are commonly referred to as a frame. As the electron beam moves across the pixels of each scan line, the beam intensity can be adjusted to vary the light produced by the screen phosphor corresponding to the pixels. The light emitted by the phosphor of the pixels creates a pattern of illuminated spots forming the video image. The intensity of the electron beam is controlled by image data stored in a section of memory called the frame buffer or refresh buffer.
2. Grating Light Valves
Another type of display system uses one or more grating light valves (“GLV”) to produce an image. GLV's are known devices, and a description can be found in (among other sources) a paper by D. M. Bloom of Silicon Light Machines, Inc., titled “The Grating Light Valve: revolutionizing display technology” (1997; available from Silicon Light Machines; and a copy of which has been filed in an Information Disclosure Statement for this application), and in an article (and therein cited references) by R. W. Corrigan and others of Silicon Light Machines, Inc., titled “An Alternative Architecture for High Performance Display” (presented at the 141st SMPTE Technical Conference and Exhibition, Nov. 20, 1999, in New York, N.Y.), the disclosures of which are incorporated herein by reference. In overview, a GLV uses a combination of reflection and diffraction of light to create an image. A GLV includes a one-dimensional array of GLV pixels, each GLV pixel including a number of microscopic “ribbons.” The ribbons for each GLV pixel can be deflected through electrostatic force to create an adjustable diffraction grating. In a non-deflected state, the ribbons reflect light. As the ribbons are deflected, the ribbons increasingly diffract light. Accordingly, by controlling the ribbons, the proportion of light that is either reflected or diffracted can be controlled for each GLV pixel. The GLV deflects the ribbons for each GLV pixel according to image data, such as pixel data received from a frame buffer.
An array of GLV pixels can create a column of visible pixels, such as 1088 pixels, typically an entire column at a time. A GLV can be used to create a vertical column of pixels in a high definition resolution image, such as a screen resolution of 1920 pixels horizontally by 1080 pixels vertically (with some of the 1088 pixels left blank or dark). By providing a GLV with pixel data representing columns of pixels in a frame, the GLV can create the frame of pixels, one column at a time, sweeping from left to right. The location of each column of pixels can be controlled external to the GLV array, such as through lenses and an adjustable mirror, rather than moving the GLV itself. A combination of three GLV's for red, green, and blue can be used to produce a color image.
3. Frame Buffers
FIG. 1A
is a representation of a screen
105
as a grid of pixels
110
. In
FIG. 1A
, for simplicity, screen
105
is only 4×4 and so only 16 pixels are shown, but a typical screen has many more pixels. One common screen resolution is high definition (“HD”) resolution, where screen resolution indicates the number of pixels in a frame and is typically given as the horizontal resolution (number of pixels in one row) versus the vertical resolution (number of pixels in one column). HD resolution is either 1920×1080 (2,073,600 total pixels per frame) or 1280×720 (921,600 pixels per frame). Herein, HD resolution refers to 1920×1080.
Returning to
FIG. 1A
, the pixels
110
are often numbered sequentially for reference. Pixel
0
is typically at the upper left.
FIG. 1B
is a representation of a memory device
150
implementing a frame buffer as a grid of memory locations
155
. Typical memory devices include SDRAM (synchronous dynamic random access memory). The actual memory device used may vary in different devices, but the memory locations for the frame buffer are typically in a contiguous block of locations with sequential addresses. Memory device
150
has a memory location
155
for storing pixel data (e.g., an intensity value) for each pixel
110
of screen
105
. In some implementations, pixel data for more than one pixel is stored at each memory location. In many conventional raster-scan systems, pixel data is stored in memory locations adjacent to one another in the same pattern as the pixels on the screen. In
FIG. 1B
, each memory location
155
is numbered with the number of the pixel (
110
from
FIG. 1A
) corresponding to the pixel data stored in that memory location
155
. For example, the pixel at the upper left of the screen is pixel 0 in FIG.
1
A and pixel data for pixel 0 is stored in the first memory location in memory device
150
, as indicated by the “0” in the upper left memory location
155
. The second memory location stores pixel data for pixel 1, the fifth memory location stores pixel data for pixel 4, and so on.
4. Pixel Rates
FIG. 2
is a representation of screen resolutions and typical data throughput requirements.
FIG. 2
shows four resolutions in respective areas: VGA resolution (640×480)
205
, XGA resolution (1024×768)
210
, SXGA resolution (1280×1024)
215
, and HD resolution (1920×1080)
220
. The pixel rate for a screen resolution is the number of pixels per second that need to be processed to maintain the screen resolution at a specified refresh rate (i.e., the number of times a complete frame is drawn to the screen per second). While pixel rates vary among implementations, the pixel rates shown in
FIG. 2
are representative. These pixel rates are given in megapixels per second (“MP/S”). For example, according to SMPTE 274M-1998 (a specification defining, among other things, pixel rates for resolutions of 1920×1080), for HD resolution
220
the pixel rate is about 150 MP/S @ 60 Hz.
FIG. 2
also shows a corresponding approximate data rate in megabytes per second (“MB/S”) for each resolution. The data rate is the number of bytes per second to be processed based on the number of bytes per pixel and the pixel rate. For example, HD resolution
220
has a data rate of 450 MB/S, at 24 bits per pixel (3 bytes). If each pixel has 32 bits of data, the data rate for HD resolution is 600 MB/S. However, the data rate of a typical 32-bit wide SDRAM running at 125 MHZ is approximately 500 MB/S. A frame buffer architecture using two 125 MHZ SDRAM's can realize a data rate of approximately 1000 MB/S.
5. Frame Buffers Using Parallel Storage in Two Memory Devices
FIG. 3A
is a representation of a frame
305
of pixels
310
divided between two memory devices. Frame
305
has only 32 pixels for simplicity, but, as noted above, a typical HD resolution frame has 2,073,600 pixels.
FIG. 3B
is a representation of a first memory device
350
and
FIG. 3C
is a representation of a second memory device
375
. Each pixel
310
in frame
305
is numbered, starting with pixel 0 in the upper

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