Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2011-05-31
2011-05-31
Rizk, Sam (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S719000
Reexamination Certificate
active
07954042
ABSTRACT:
For checking an address decoder of a data memory, from a record of addresses of the data memory, designated as base addresses, one after another each base address is selected, and the following steps are executed for the respectively selected base address:a) determining the content of the base address; andb) selecting an address having the Hamming distance 1 from the base address, designated as the Hamming address; and then:c) changing the content of the Hamming address selected in step b); and then:d) reading the base address and detecting an error of the address decoder if the content read differs from that determined in step a); ande) recovering the content of the Hamming address.
REFERENCES:
patent: 2006/0077750 (2006-04-01), Pescatore
patent: 2006/0156134 (2006-07-01), Mukherjee et al.
patent: 43 17 175 (1994-11-01), None
patent: 1001432 (2000-05-01), None
Manoj Sachdev “Testing and Testability Techniques for Open Defects in RAM Address Decoders”, 1996, IEEE, 7 Pages, ED&TC.
Luigi Dilillo et al., “Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders”, 2003, IEEE, 6 Pages, Proceedings of the 12thAsian Test Symposium.
Benoit Nadeau-Dostie et al., “Serial Interfacing for Embedded-Memory Testing”, 1990, IEEE Design & Test of Computers, pp. 52-63.
Shreekanth Moorthy, “Integrating the CAD Model With Dynamic Simulation: Simulation Data Exchange”, 1999, pp. 276-280, Proceedings of the 1999 Winter Simulation Conference.
U. Roegoderer et al., “A Concept for Automatical Layout Generation”, 1995, IEEE, pp. 800-805, IEEE International Conference on Robotics and Automation.
Manfred Weck et al., “Abteilungsubergreifendes Projektieren kimplexer Maschinen and Anlagen”, Oct. 1995, pp. 54-58, Integrierte Produktion English translation of summary/abstract is provided herewith.
Todd McCall, “IBM and Dassault Systemes Launch CATIA Version 5 Release 6”, May 2001, IBM, Online, COE NewsNet, http://www.coe.org/coldfusion
ewsnet/may01/technology.cfm.
Boehl Eberhard
Schmidt-Grethe Karsten
Seydel Gunter
Kenyon & Kenyon LLP
Rizk Sam
Robert & Bosch GmbH
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