Check pattern for via-hole opening examination

Details Check pattern for via-hole opening examination Check pattern for via-hole opening examination

1998-03-04

2000-10-03

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257774, 257621, 257623, H01L 2348, H01L 2352, H01L 2940

Patent

active

061277339

ABSTRACT:
To provide a check pattern whereby whether via-hole openings are made correctly or not can be examined without needing high precision positioning of the via-holes, a check pattern of the invention comprises: a check wiring (3) configured on a semiconductor substrate (2), an insulation film (4) formed on the semiconductor substrate (2) to cover the check wiring; and a pair of via-holes (6) each configured at each end of the check wiring (3), said each (6) positioned slightly shifted inversely with each other from a center line in a width direction of the check wiring (3), and a bottom of said each (6) being positioned to traverse both the check wiring (3) and the insulation film (4).

REFERENCES:
patent: 5565697 (1996-10-01), Asakawa et al.
patent: 5619072 (1997-04-01), Mehta
patent: 5668413 (1997-09-01), Nanjo
patent: 5721453 (1998-02-01), Imai et al.
patent: 5825059 (1998-10-01), Kuroda
patent: 5838023 (1998-11-01), Goel et al.
"the National Technology Roadmap for Semiconductors"; p. 98; Table 22: Interconnect Design Ground Rules and Assumptions.

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