Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2009-07-24
2010-11-30
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C250S492230, C250S492200, C250S492300, C250S492220, C250S492100, C438S016000, C430S005000, C430S296000, C430S311000, C257SE21530
Reexamination Certificate
active
07844941
ABSTRACT:
When a space, sandwiched by large patterns having a predetermined size or more, is exposed using a charged particle beam, the space sandwiched by the large patterns is exposed using a common block mask having the space and edge portions of the large patterns on both sides of the space, and portions other than the edge portions of the large patterns on both sides are exposed by a variable rectangular beam or by using another block mask.
REFERENCES:
patent: 6415432 (2002-07-01), Saito et al.
patent: 6541783 (2003-04-01), Robinson et al.
patent: 6901576 (2005-05-01), Liebmann et al.
patent: 2000323377 (2000-11-01), None
patent: 2001052999 (2001-02-01), None
patent: 2001168006 (2001-06-01), None
patent: 2004200275 (2004-07-01), None
Fujitsu Semiconductor Limited
Garbowski Leigh Marie
Westerman Hattori Daniels & Adrian LLP
LandOfFree
Charged particle beam exposure method and charged particle... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Charged particle beam exposure method and charged particle..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charged particle beam exposure method and charged particle... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4180645