Charge-trapping semiconductor memory device

Details Charge-trapping semiconductor memory device Charge-trapping semiconductor memory device

2006-05-30

2006-05-30

Eckert, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S330000, C257S332000, C257S334000, C438S278000, C438S216000, C438S261000, C438S591000, C438S268000

Reexamination Certificate

active

07053447

ABSTRACT:
Memory cells are formed by preferably cylindrical recesses at the main surface of a semiconductor substrate, containing a memory layer sequence at sidewalls and a gate electrode and being provided with upper and lower source/drain regions connected in columns to first and second bit lines. Word lines are arranged above the first and second bit lines and connected to rows of gate electrodes. The vertical transistor structure facilitates a further shrinking of the cells and enables a required minimum effective channel length.

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Eitan, B., et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.

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