Charge-trapping memory device including high permittivity...

Details Charge-trapping memory device including high permittivity... Charge-trapping memory device including high permittivity...

2006-05-23

2006-05-23

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S316000, C257S320000, C257S321000, C257S322000, C257S326000

Reexamination Certificate

active

07049651

ABSTRACT:
The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.

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Yeh, C.C., et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,” IEEE, 2002.

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