Charge-trapping memory cell and method for production

Details Charge-trapping memory cell and method for production Charge-trapping memory cell and method for production

2007-11-20

2007-11-20

Doan, Theresa (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S317000

Reexamination Certificate

active

11000350

ABSTRACT:
The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer sequence is arranged on the fins. Wordlines are arranged across the fins, and source/drain regions are located in the fins between the wordlines and at the ends of the fins. There are preferably self-aligned contact areas of the source/drain regions at the ends of the fins, each contact area being common to the fins of one of said pairs. Select transistors and select lines are provided for the first and second fins individually to enable a separate addressing of the memory cells.

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patent: 102 20 923 (2003-11-01), None
Specht, M., et al., “Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications,” 2004 Symposium on VLSI Technology, pp. 244-245.
Anil, K.G., et al., “Layout Density Analysis of FinFETs,” Proceedings of the 33rdEuropean Solid-State Device Research, vol., Iss., Sep. 16-18, 2003, pp. 139-142.
Sung, S-K., et al., “Fabrication and Program/Erase Characteristics of 30-nm SONOS Nonvolatile Memory Devices,” IEEE Transactions on Nanotechnology, vol. 2, No. 4, Dec. 2003, pp. 258-264.

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