Charge trapping memory cell

Details Charge trapping memory cell Charge trapping memory cell

2006-08-08

2006-08-08

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Implanting to form insulator

C438S424000, C257S315000, C257S326000

Reexamination Certificate

active

07087500

ABSTRACT:
A memory cell includes a channel region between source/drain regions at the top side of a semiconductor body and is provided, transversely with respect to the longitudinal direction, with a bulge formed in the semiconductor material. This results in a uniform distribution of the strength of a radially directed electric field and avoids field strength spikes at lateral edges of the channel region. A storage layer sequence is situated between the channel region and the gate electrode as part of a word line.

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Park, et al., “Fabrication of Body-Tied FinFETs (Omega MOSFETs) Using Bulk Si Wafers,” 2003 Symposium on VLSI Technology Digest of Technical Papers, Jun. 10-12, 2003, pp. 135-136.

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