Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2005-02-01
2005-02-01
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C365S159000
Reexamination Certificate
active
06849483
ABSTRACT:
A charge trapping device, and a method of forming the same is disclosed. Charge traps are optimally distributed through a trapping region based on controlling various conventional processing operations, such as an implant, an anneal, an insulator film deposition, and the like. In some embodiments, FETs can be configured to include a negative differential resistance (NDR) characteristic when they utilize a particular charge trap energy and distribution.
REFERENCES:
patent: 3588736 (1971-06-01), McGroddy
patent: 3903542 (1975-09-01), Nathanson et al.
patent: 3974486 (1976-08-01), Curtis et al.
patent: 4047974 (1977-09-01), Harari
patent: 4143393 (1979-03-01), DiMaria et al.
patent: 4644386 (1987-02-01), Nishizawa et al.
patent: 4806998 (1989-02-01), Vinter et al.
patent: 4945393 (1990-07-01), Beltram et al.
patent: 5021841 (1991-06-01), Leburton et al.
patent: 5023836 (1991-06-01), Mori
patent: 5032891 (1991-07-01), Takagi et al.
patent: 5084743 (1992-01-01), Mishra et al.
patent: 5093699 (1992-03-01), Weichold et al.
patent: 5130763 (1992-07-01), Delhaye et al.
patent: 5162880 (1992-11-01), Hazama et al.
patent: 5189499 (1993-02-01), Izumi et al.
patent: 5357134 (1994-10-01), Shimoji
patent: 5390145 (1995-02-01), Nakasha et al.
patent: 5442194 (1995-08-01), Moise
patent: 5448513 (1995-09-01), Hu et al.
patent: 5455432 (1995-10-01), Hartsell et al.
patent: 5463234 (1995-10-01), Toriumi et al.
patent: 5477169 (1995-12-01), Shen et al.
patent: 5523603 (1996-06-01), Fishbein et al.
patent: 5543652 (1996-08-01), Ikeda et al.
patent: 5552622 (1996-09-01), Kimura
patent: 5606177 (1997-02-01), Wallace et al.
patent: 5633178 (1997-05-01), Kalnitsky
patent: 5689458 (1997-11-01), Kuriyama
patent: 5698997 (1997-12-01), Williamson, III et al.
patent: 5705827 (1998-01-01), Baba et al.
patent: 5732014 (1998-03-01), Forbes
patent: 5761114 (1998-06-01), Bertin et al.
patent: 5770958 (1998-06-01), Arai et al.
patent: 5773996 (1998-06-01), Takao
patent: 5798965 (1998-08-01), Jun
patent: 5804475 (1998-09-01), Meyer et al.
patent: 5843812 (1998-12-01), Hwang
patent: 5869845 (1999-02-01), Van der Wagt et al.
patent: 5883549 (1999-03-01), De Los Santos
patent: 5883829 (1999-03-01), Van der Wagt
patent: 5895934 (1999-04-01), Harvey et al.
patent: 5903170 (1999-05-01), Kulkarni et al.
patent: 5907159 (1999-05-01), Roh et al.
patent: 5936265 (1999-08-01), Koga
patent: 5945706 (1999-08-01), Jun
patent: 5953249 (1999-09-01), Van der Wagt
patent: 5959328 (1999-09-01), Krautschneider et al.
patent: 5962864 (1999-10-01), Leadbeater et al.
patent: 6015739 (2000-01-01), Gardner et al.
patent: 6015978 (2000-01-01), Yuki et al.
patent: 6075265 (2000-06-01), Goebel et al.
patent: 6077760 (2000-06-01), Fang et al.
patent: 6084796 (2000-07-01), Kozicki et al.
patent: 6091077 (2000-07-01), Morita et al.
patent: 6097036 (2000-08-01), Teshima et al.
patent: 6104631 (2000-08-01), El-Sharawy et al.
patent: 6128216 (2000-10-01), Noble, Jr. et al.
patent: 6130559 (2000-10-01), Balsara et al.
patent: 6150242 (2000-11-01), Van der Wagt et al.
patent: 6184539 (2001-02-01), Wu et al.
patent: 6205054 (2001-03-01), Inami
patent: 6222766 (2001-04-01), Sasaki et al.
patent: 6225165 (2001-05-01), Noble, Jr. et al.
patent: 6246606 (2001-06-01), Forbes et al.
patent: 6261896 (2001-07-01), Jun
patent: 6294412 (2001-09-01), Krivokapic
patent: 6301147 (2001-10-01), El-Sharawy et al.
patent: 6303942 (2001-10-01), Farmer
patent: 6310799 (2001-10-01), Duane et al.
patent: 6353251 (2002-03-01), Kimura
patent: 6396731 (2002-05-01), Chou
patent: 6404018 (2002-06-01), Wu et al.
patent: 6424174 (2002-07-01), Nowak et al.
patent: 20010013621 (2001-08-01), Nakasato
patent: 20010019137 (2001-09-01), Koga et al.
patent: 20010024841 (2001-09-01), Noble, Jr. et al.
patent: 20010053568 (2001-12-01), Deboy et al.
patent: 20020017681 (2002-02-01), Inoue et al.
patent: 20020048190 (2002-04-01), King
patent: 20020054502 (2002-05-01), King
patent: 20020057123 (2002-05-01), King
patent: 20020063277 (2002-05-01), Ramsbey et al.
patent: 20020066933 (2002-06-01), King
patent: 20020067651 (2002-06-01), King
patent: 20020076850 (2002-06-01), Sadd et al.
patent: 20020093030 (2002-07-01), Hsu et al.
patent: 20020096723 (2002-07-01), Awaka
patent: 20020100918 (2002-08-01), Hsu et al.
patent: 20020109150 (2002-08-01), Kajiyama
patent: 20020151123 (2002-10-01), Torii
patent: 20030067030 (2003-04-01), Torii
patent: 0747961 (1996-12-01), None
patent: 0748940 (1996-12-01), None
patent: 0655788 (1998-01-01), None
patent: 1050964 (2000-11-01), None
patent: 1085656 (2001-03-01), None
patent: 1107317 (2001-06-01), None
patent: 0526897 (2001-11-01), None
patent: 1168456 (2002-01-01), None
patent: 1204146 (2002-05-01), None
patent: 8018033 (1996-01-01), None
patent: 2001 01015757 (2001-01-01), None
patent: WO 9003646 (1990-04-01), None
patent: WO 9963598 (1999-04-01), None
patent: WO 0041309 (2000-07-01), None
patent: WO 0165597 (2001-09-01), None
patent: WO 0169607 (2001-09-01), None
patent: WO 0188977 (2001-11-01), None
patent: WO 0199153 (2001-12-01), None
Barlow, P.S. et al., “Negative differential output conductance of self-heated power MOSFETs,” IEE Proceedings-I Solid-State and Electron Devices, vol. 133, Part I, No. 5, October 1986, pp. 177-179.
Neel, O. L, et al., “Electrical Transient Study of Negative Resistance in SOi MOS Transistors,” Electronics Letters, vol. 25, No. 1, pp. 73-74, Jan. 1990.
Mohan, S. et al., “Ultrafast Pipelined Adders Using Resonant Tunneling Transistors,” IEE Electronics Letters, vol. 27, No. 10, May 1991, pp. 830-831.
Zhang, J.F. et al., “Electron trap generation in thermally grown SIO2 under Fowler-Nordheim stress,” J. Appl. Phys. 71 (2), Jan. 15, 1992, pp. 725-734.
Zhang, J.F. et al., “A quantitative investigation of electron detrapping in SiO2 under Fowler-Nordheim stress,” J. Appl. Phys. 71 (12), Jun. 15, 1992, pp. 5989-5996.
Zhang, J.F. et al., “A comparative study of the electron trapping and thermal detrapping in SiO2 prepared by plasma and thermal oxidation,” J. Appl. Phys. 72 (4), Aug. 15, 1992, pp. 1429-1435.
Luryi, S. et al., “Collector-Controlled States in Charge injection Transistors,” SPIE-92 Symposium, pp. 1-12, 1992.
Luryi, S. et al., “Collector-Controlled States and the Formation of Hot Electron Domain-in Real-Space Transfer Transistors,” AT&T Bell Laboratories, pp. 1-7, 1992.
Luryi, S. et al., “Light-emitting Logic Devices based on Real Space Transfer in Complementary InGaAs/InAlAs Heterostructures”, In “Negative Differential Resistance and Instabilities in 2D Semiconductors”, ed. by N. Balkan, B. K. Ridley, and A. J. Vickers, NATO ASI Series [Physics] B 307, pp. 53-82, Plenum Press (New York 1993).
Mohan, S, et al., “Logic Design Based on Negative Differential Resistance Characteristics of Quantum Electronic Devices,” IEE Proceedings-G: Electronic Devices, vol. 140, No. 6, Dec. 1993, pp. 383-391.
Mohan, S. et al., “Ultrafast Pipelined Arithmetic Using Quantum Electronics Devices,” IEE Proceedings-E: Computers and Digital Techniques, vol. 141, No. 2, Mar. 1994, pp. 104-110.
Chan, E. et al., “Compact Multiple-Valued Multiplexers Using Negative Differential Resistance Devices,” IEEE Journal of Solid-State Circuits, vol. 31, No. 8, Aug. 1996, pp. 1151-1156.
Chan, E. et al., “Mask Programmable Multi-Valued Logic Gate Using Resonant Tunnelling Diodes,” IEE Proceedings-Circuits Devices Syst., vol. 143, No. 5, Oct. 1996, pp. 289-294.
Shao, Z. et al., “Transmission Zero Engineering in Lateral Double-Barrier Resonant Tunneling Devices,” Dept. Of Electrical Engineering, University of Notre Dame, pp. 1-7 (1996).
Goldhaber-Gordon, David et al., “Overview of nanoelectronic devices,” Proc. IEEE, 85(4), Apr. 1997, pp. 521-540.
Koester, S. J. et al., “Negative Differential Conductance in Lateral Double-Barrier Transistors Fabricated In Strained Si Quantum Wells,” Applied Physics Letters, vol. 70, No
Gross J. Nicholas
Kilday Lisa
Pert Evan
Progressant Technologies, Inc.
LandOfFree
Charge trapping device and method of forming the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Charge trapping device and method of forming the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charge trapping device and method of forming the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3471017