Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2008-03-11
2008-03-11
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185030, C365S185180
Reexamination Certificate
active
07342827
ABSTRACT:
Disclosed herein is a charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same. The charge trap-type 3-level non-volatile semiconductor memory device includes a memory array including a plurality of memory elements, each capable of storing data in at least two charge trap regions depending on the direction of current flow, and a page buffer driven to map three data bits to threshold voltage groups of the two charge trap regions. The charge trap-type non-volatile semiconductor memory device has charge trap regions each storing 1.5 bits of data. That is, a single memory element has charge trap regions for storing 3 bits of data, thereby improving device integration while maintaining a high operating speed during programming and reading operations.
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English language abstract of Korean Publication No. 2005-0040667.
Choi Jung-dal
Park Ki-Tae
Marger & Johnson & McCollom, P.C.
Nguyen Hien
Phung Anh
Samsung Electronics Co,. Ltd.
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