Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Physical stress responsive
Reexamination Certificate
2001-04-20
2002-07-30
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
Physical stress responsive
C438S396000, C438S734000, C438S735000, C365S183000, C257S221000, C257S239000
Reexamination Certificate
active
06426238
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present inventions relates to a CCD (Charge Coupled Device)-type charge transfer device driven by two phase pulses and to a solid image pickup apparatus using such charge transfer devices, and in particular, relates to an improvement for increasing the charge transfer efficiency adjacent to an output portion of the charge transfer device.
2. Description of the Related Art
FIG. 6
is a diagram showing the structure of a general interline transfer-type solid image pickup apparatus. In
FIG. 6
, reference numeral
101
denotes a photodiode,
102
denotes a vertical CCD register which receives and transfers a charge from the photodiode
101
,
103
denotes a horizontal CCD register which receives and transfers the charge from the vertical CCD register
102
,
104
denotes a charge detection portion which detects the charge transferred from the horizontal CCD register
103
, and
105
denotes an output amplifier. Here, a rectangular portion enclosed by a broken line shows a pixel
106
.
For an image pickup apparatus used for a digital still camera such as a digital steal camera, reduction of the power consumption is indispensable. In the case of a two dimensional CCD image sensor, the power consumption of the horizontal CCD registers is particularly large, and the power consumption increases as the speed of the horizontal CCD registers increases. In order to reduce the power consumption, the reduction of the driving voltage of the horizontal CCD register is an critical problem to be solved.
One of the measures to solve the above-described problem is disclosed in Japanese Unexamined Patent Application, First Publication No. 11-17163. This disclosure involves a method in which, in a CCD-type register having two layered electrodes and a two phase driving system, generation of the potential drop under the boundary between two electrodes is suppressed by forming an n-type low concentration semiconductor layer in a self-aligning manner.
FIG. 7
is a plan view showing the structure of the output portion of the conventional horizontal CCD registers, and
FIG. 8
shows a cross-sectional view along the line II—II. As shown in
FIG. 7
, above the charge transfer channel
111
, a plurality of storage electrodes
112
a,
112
b,
112
c
, . . . and a plurality of barrier electrodes
113
a,
113
b,
113
c
, . . . are formed. Here, to simplify the description, a pair of charge transfer electrodes composed of a storage electrode
112
a
and a barrier electrode
113
a,
disposed at the most left side of
FIG. 7
, is called horizontal terminal electrodes and the other pairs of charge transfer electrodes are simply called horizontal electrodes.
An output electrode
114
is disposed adjacent to the horizontal terminal storage electrode
112
a.
At one terminal of the output gate electrode
114
, a floating diffusion layer
115
, which constitutes a charge detection portion
104
, is formed, and the floating diffusion layer
115
is connected to the output amplifier
105
. At one side of the floating diffusion layer
115
, a reset gate electrode
116
is provided, and at one side of the reset gate electrode
116
, a reset drain
117
is provided. Each adjoining pair of storage electrodes
112
a,
112
b,
112
c
, . . . , and barrier electrodes
113
a,
113
b,
113
c
, . . . are connected to one metal wire
118
and the other metal wire
119
alternatively.
Two phase driving pulses &phgr;H
1
and &phgr;H
2
are respectively input into one metal wire
118
and the other metal wire
119
. A direct-current (dc) voltage VOG is applied to the output gate
114
, a reset pulse &phgr;R is input into the reset gate electrode
116
, and a dc voltage VRG is applied to the reset drain
117
.
Next, the cross-sectional structure shown in
FIG. 8
is explained in the order of the manufacturing process.
FIG. 9
shows a manufacturing method of the conventional charge transfer device. As shown in
FIG. 9A
, an n
−
-type semiconductor well
121
having an impurity concentration of 8×10
16
cm
−3
is formed with a thickness of 0.5 &mgr;m on a p-type silicon substrate
120
having an impurity concentration of 1×10
15
cm
−3
, and a first insulating film
122
is formed with a thickness of 100 nm on the surface of the n
−
-type semiconductor well
121
by an oxidation process such as thermal oxidization. Subsequently, as shown in
FIG. 9B
, a first polycrystalline silicon film is deposited with a thickness of 300 nm and the barrier electrodes
113
a,
113
b,
113
c
, . . . and the output gate electrode
114
and reset gate electrode
116
are formed by patterning the first polycrystalline silicon film.
Subsequently, as shown in
FIG. 9C
, an approximately 100 nm thick second insulating film
123
is formed on the n
−
-type semiconductor well
121
by an oxidation process such as thermal oxidization, and a third insulating film
124
is formed on the side surfaces of the barrier electrodes
113
a,
113
b,
113
c
, . . . , the output gate electrode
114
, and the reset gate electrode
116
by an accelerating oxidation of the polycrystalline silicon. Subsequently, a resist film is coated thereon, a resist pattern
125
is formed by photolithography, and n
−
-type semiconductor regions
126
a,
126
b,
126
c
, . . . are formed by phosphorus ion implantation. Here, the first polycrystalline silicon layer and the third insulating layer serve as the mask for the ion implantation.
Subsequently, as shown in
FIG. 9D
, a 300 nm thick second polycrystalline silicon film is deposited and a plurality of charge electrodes
112
a,
112
b,
112
c
, . . . are formed by patterning the film using photolithography. Subsequently, as shown in
FIG. 9E
, an n
+
-type semiconductor region
127
having an impurity concentration of 1×10
20
cm
−3
is formed with a thickness of 0.3 &mgr;m and then an interlayer insulating film
128
is formed. Subsequently, as shown in
FIG. 9F
, a through hole (not shown) is formed, an aluminum film (not shown) is deposited, and by patterning the aluminum film using photolithography, two metal conducive lines
118
and
119
are formed. The first polycrystalline silicon film, the second polycrystalline silicon, and n
+
-type semiconductor region
127
are respectively connected to those lines. The charge transfer device is obtained by the above-described manufacturing process, and the structure shown in
FIG. 9F
becomes the same as that shown in
FIG. 8
As shown in
FIG. 7
, although the channel widths W
1
of general CCD registers are 10 to 50 &mgr;m, the channel width W
2
in the vicinity of the horizontal terminal electrode is formed as narrow as 5 to 10 &mgr;m. The reason for this narrow channel width is that it is necessary to minimize the area of the floating diffusion layer in order to increase the charge detecting sensitivity of the charge detection portion
104
. In general when the channel width is formed narrower in the charge transfer direction, the transfer electric field decreases and the charge transfer efficiency decreases as the channel width becomes narrower.
FIG. 10
is a typical diagram showing a schematic potential distribution in the vicinity of the output portion of the conventional horizontal CCD register. This figure illustrates a case of charge transfer by two phase driving pulses &phgr;H
1
and &phgr;H
2
. The signal charge is transferred from the right side to the left side of the figure. The bold solid lines A indicate the state in which the &phgr;H
1
is at a low level, &phgr;H
2
is at a high level, and &phgr;R is at a low level. In contrast, the thin line B in the figure indicates the state in which the &phgr;H
1
is at a high level, &phgr;H
2
is at a low level, and &phgr;R is at a high level; thus, the signal charge stored in the floating diffusion layer
115
is discharged through the reset gate electrode
116
to the reset drain
117
. Simultaneously, the signal charge for the next bit stored in the previous stage is transferred to the horizontal terminal
Elms Richard
Luu Pho
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