Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Charge transfer device
Reexamination Certificate
2000-04-07
2002-04-30
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Charge transfer device
C438S146000, C438S148000, C438S060000, C438S077000, C438S079000
Reexamination Certificate
active
06380005
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charge transfer device and method for manufacturing the same, and more specifically to a charge transfer device of the two-layer electrode, two-phase drive type having charge storage regions and charge barrier regions formed in self-alignment with transfer electrodes, and a method for manufacturing the same.
2. Description of Related Art
At present, an image input device having a large number of pixels and a high degree of portability, such as a highly definition television camera and a digital still camera, is now actively developed.
For this image input device, it has become indispensable to develop a solid state image pickup device having a reduced power consumption. In particular, it has become a significant object to lower a drive voltage of a horizontal charge transfer section, which has a high drive frequency in the solid state image pickup device.
In general, the horizontal charge transfer section is constituted of a two-layer electrode, two-phase drive type charge transfer device, since it is necessary to transfer signal charges at a high speed.
Now, referring to
FIGS. 1A
to
1
G, there are shown diagrammatic sectional views for illustrating a process for manufacturing the prior art two-layer electrode, two-phase drive type charge transfer device, which is disclosed in, for example, C. K. Kim, “TWO-PHASE CHARGE COUPLED LINEAR IMAGING DEVICES WITH SELF-ALIGNED IMPLANTED BARRIER”, IEDM Technical Digest, 1974, pp55-58 (the content of which is incorporated by reference in its entirety into this application) and Japanese Patent Application Pre-examination Publication No. JP-A-62-071273, (an English abstract of JP-A-62-071273 is available from the Japanese Patent Office and the content of the English abstract of JP-A-62-071273 is incorporated by reference in its entirety into this application).
First, as shown in
FIG. 1A
, at a principal surface of a P-type semiconductor substrate
101
such as a P-type silicon substrate having an impurity concentration of about 1×10
15
cm
−3
, there is formed an N-type semiconductor region
102
having the conductivity opposite to that of the substrate and having an impurity concentration of about 1×10
17
cm
−3
, and also having the depth of about 0.5 &mgr;m from the principal surface of the P-type semiconductor substrate
101
. By a thermal oxidation, a first insulator film
103
having a thickness of about 100 nm is formed on a surface of the an N-type semiconductor region
102
.
Next, as shown in
FIG. 1B
, on the first insulator film
103
, a plurality of first charge transfer electrodes . . . ,
104
i
,
104
j
,
104
k
,
104
l
, . . . , (represented by
104
) are formed of polysilicon by a low pressure CVD (chemical vapor deposition) process to have a thickness of about 300 nm and to be located with a predetermined intervals.
Succeedingly, after the first insulator film
103
is selectively removed by using the first charge transfer electrodes
104
as a mask, a thermal oxidation is carried out again so that, as shown in
FIG. 1C
, a second insulator film
105
having a thickness of about 100 nm is formed on the surface of the N-type semiconductor region
102
, and a third insulator film
106
having a thickness of about 200 nm because of an enhanced oxidation of the polysilicon is formed on a top surface and a side surface of each of the first charge transfer electrodes
104
. Alternatively, by the CVD process causing SiH
4
gas and H
2
O gas to react, a second insulator film
105
having a thickness of about 100 nm is formed on the surface of the N-type semiconductor region
102
, and a third insulator film
106
having a thickness of about 100 nm is formed on a top surface and a side surface of each of the first charge transfer electrodes
104
.
Then, as shown in
FIG. 1D
, an impurity (for example, boron) of the conductivity opposite to that of the N-type semiconductor region
102
is selectively introduced using the first charge transfer electrodes
104
and the third insulator film
106
as a mask, by an ion-implantation having an incident angle of 0 (zero) degree, namely, perpendicular to the surface of the substrate, so that N
−−
semiconductor regions
108
having an impurity concentration of about 8×10
16
cm
−3
are formed in self-alignment with the first charge transfer electrodes
104
and the third insulator film
106
.
Thereafter, as shown in
FIG. 1E
, on the second insulator film
105
and the third insulator film
106
, a plurality of second charge transfer electrodes . . . ,
109
i
,
109
j
,
109
k
,
109
l
, . . . , (represented by
109
) are formed of polysilicon by the low pressure CVD process to have a thickness of about 300 nm, and located with a predetermined intervals. Each of the second charge transfer electrodes
109
is formed to cover the N
−−
semiconductor region
108
between each pair of adjacent first charge transfer electrodes
104
, and to partially overlap on a near side end of each of the pair of adjacent first charge transfer electrodes
104
.
Succeedingly, as shown in
FIG. 1F
, an interlayer insulator film
110
is formed to cover the whole. Then, not-shown through-holes are formed, and a not-shown aluminum film is deposited and patterned so that, as shown in
FIG. 1G
, a pair of metal interconnections
111
-
1
and
111
-
2
are alternately connected to transfer electrode pairs, each of which is composed of one first charge transfer electrode
104
(for example
104
i
) and one adjacent second charge transfer electrode
109
(for example
109
i
). In the shown example, transfer electrode pairs
104
j
+
109
j
,
104
l
+
109
l
are connected to the metal interconnections
111
-
1
and transfer electrode pairs
104
i
+
109
i
,
104
k
+
109
k
are connected to the metal interconnections
111
-
2
.
In the above mentioned prior art charge transfer device of the two-layer electrode, two-phase drive type, signal charges can be transferred from the right to the left in the drawing, by driving the pair of metal interconnections
111
-
1
and
111
-
2
with a pair of transfer clock pulses &phgr;
1
and &phgr;
2
having the amplitude of about 5V and having the phase different from each other by 180 degrees as shown in
FIG. 2
, respectively.
However, the following problems have been encountered in the above mentioned prior art charge transfer device of the two-layer electrode, two-phase drive type. Since the N-type semiconductor region having the same impurity concentration is formed directly under the first charge transfer electrode and under the gap between the first charge transfer electrode and the second charge transfer electrode, in particular when it is attempted to transfer the signal charge with a low drive voltage (for example on the order of 3V), since the third insulator film
3
under the second charge transfer electrode in the area of the gap effectively acts as a thick insulator, a potential recess is easy to occur, and therefore, the transfer efficiency drops.
Referring to
FIG. 3
, there is shown a diagram for illustrating the problem of the above mentioned prior art charge transfer device of the two-layer electrode, two-phase drive type when the drive voltage is made low. In the diagram of
FIG. 3
, a potential diagram is combined with a sectional view of the charge transfer device in order to indicate a position in the coordinate. In addition, the dotted line indicates a potential diagram when the drive voltage is high (for example on the order of 5V) and the solid line indicates a potential diagram when the drive voltage is low (for example on the order of 3V).
The potential recess occurring due to the gap between the first transfer electrode and the second transfer electrode is modulated by a fringe electric field and therefore is suppressed, if a potential difference between portions directly under adjacent transfer electrodes is large. Namely, as shown in
FIG. 3
, when the drive voltage of the charge transfe
Luu Chuong A
McGinn & Gibb PLLC
NEC Corporation
Smith Matthew
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