Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-04-12
2001-07-31
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185300
Reexamination Certificate
active
06269026
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and, more particularly, to a method for charging wordlines in flash electrically erasable programmable read-only memory (flash EEPROM) devices.
BACKGROUND OF THE INVENTION
A flash memory is a storage device that is capable of retaining stored information in the absence of continuous power. The information is stored in a plurality of flash transistors that are electrically connected and formed on a silicon substrate. A flash transistor is typically referred to as a cell and includes a source, a drain, a floating gate and a control gate. Flash memory devices are formed by rows and columns of flash transistors that form a flash transistor array. As known in the art, the control gates of the cells are electrically connected with a respective wordline and the drains of the cells are electrically connected with a respective bitline. The source of each cell is electrically connected with a common source line.
The information stored in each particular cell represents a binary one or zero, as known in the art. To perform a program, read or erase operation of a particular cell in the array, a respective voltage is applied to a predetermined wordline, bitline and source line. By applying the voltages to a select bitline column and a select wordline row, an individual cell can be read or programmed.
To program a respective cell, the control gate and the drain of the cell are raised to respective predetermined programming voltages and the source is grounded. When the programming voltages are placed on the control gate and the drain, hot electrons are generated that are injected onto the floating gate where they are trapped forming a negative charge. This electron transfer mechanism is often referred to as Channel Hot Electron (CHE) injection in the semiconductor industry. When the programming voltages are removed, the negative charge on the floating gate is maintained, thereby raising the threshold voltage of the cell. The threshold voltage is used when the cell is read to determine if it is in a charged (programmed) or an uncharged (un-programmed) state.
Cells are read by applying a predetermined voltage to the control gate and the drain, grounding the source of the cell and then sensing the current in the bitline. If the cell is programmed, the threshold voltage will be relatively high and the bitline current will be zero or at least relatively low when a read voltage is applied between the control gate and the source of the cell. If the cell is erased, the threshold voltage will be relatively low and the bitline current will be relatively high when the same read voltage is applied.
In contrast to the programming procedure, flash memory devices are typically bulk-erased, so that all of the cells in a memory sector are simultaneously erased. A memory sector describes the number of wordlines and bitlines in the array and can be formed to include 512 wordlines and 1024 bitlines in a 64-kbyte array. Erasing memory sectors can be performed in several ways involving the application of a set of predetermined voltages to the common source line, the bitlines and the wordlines. This causes electron tunneling from the floating gate to the source through Fowler-Nordheim (F-N) tunneling, which removes the negative charge from the floating gate of the cells in the memory sector.
Cells are typically erased by application of an erase pulse to the memory sector targeted for erasure for a predetermined time. Ideally, each cell in the memory sector requires the same amount of time to remove electrons from the floating gate. In reality, erase times among the cells within the memory sector vary and some of the cells subjected to the erase pulse may become over-erased. The threshold voltage of an over erased cell is lowered to the point that it can cause excessive leakage current in the bitline. Excessive leakage current can prevent proper reading of the programmed cells in the bitline of the memory sector.
It is known in the art that to correct for excessive leakage current, the bitlines are verified during an Automatic Program Disturb Erase Verify (APDEV) operation that occurs automatically as part of an Automatic Program Disturb Erase (APDE) operation. The APDEV operation verifies that each bitline in a particular sector does not contribute excessive leakage current above a predetermined reference current and takes corrective action if necessary. During the APDEV operation, a bias voltage is applied to all the wordlines in the sector and each bitline in the sector is sequentially sensed for current above the reference current. If the bitline current is above the reference current, a stress operation is performed on all the cells in the bitline. A stress operation is known in the art as a soft program that mainly affects the over-erased cells by raising their threshold voltage. After the stress operation, the bitline current is sensed again and the stress operation is repeated if necessary until the current sensed on the bitline during the APDEV operation is below the reference current.
The time required to perform the APDEV operation is increased by the amount of time required to generate the bias voltage on the wordlines. The wordlines are charged up to the bias voltage and due to their capacitive nature, the time to charge the wordlines is dependent on the magnitude of voltage and current available. Typically, all wordlines in the memory sector are charged to the bias voltage simultaneously during the APDEV operation.
The incorporation of lower supply voltages for flash memory devices creates an undesirable increase in the wordline voltage charge time during the APDEV operation. If the bias voltage required to verify the bitlines during the APDEV operation cannot be reached, the current sensed on the bitlines will not correspond to the reference current and the bitlines may not properly verify. Further, the magnitude of capacitance created by the control gate capacitance of the cells on each wordline adds to the difficulty of maintaining the wordline voltage charge time. Since the APDEV operation typically runs multiple times in order to correct the over-erased cells, the increased wordline charge time during the APDEV operation will be multiplied as well.
For the foregoing reasons, a need exists to provide a way of charging the wordlines in a memory sector to the bias voltage so that the bitlines in a memory sector can be verified during the APDEV operation in the desired time irrespective of the supply voltage or cell size.
SUMMARY OF THE INVENTION
The present invention discloses a flash memory wordline charging architecture that is used to charge a plurality of wordlines to a predetermined bias voltage during an APDEV operation. The preferred flash memory includes a charge share circuit and a temperature compensated bias generator circuit that are electrically connected with at least one pass gate. In addition, the charge share circuit is electrically connected with the temperature compensated bias generator circuit. The pass gates are electrically connected with the wordlines in a respective memory sector of the flash memory. During operation, the charge share circuit and the temperature compensated bias generator circuit provide respective charging voltages that are directed by the pass gates to the wordlines during the APDEV operation.
The present invention further discloses a method of charging wordlines to the predetermined bias voltage during the APDEV operation in the flash memory. During the APDEV operation, the charge share circuit generates a first predetermined voltage that is directed to the wordlines through the pass gates for a first predetermined amount of time. The first predetermined voltage is used to charge the wordlines to a base voltage in a rather short period of time. After the charge share circuit charges the wordlines to the base voltage, the temperature compensated bias generator circuit then generates a second predetermined voltage.
The second predetermined voltage is directed with
Bautista, Jr. Edward V.
Venkatesh Bhimachar
Advanced Micro Devices , Inc.
Le Vu A.
Phung Anh
Wagner , Murabito & Hao LLP
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