Charge sharing reduction by applying intrinsic parallelism...

Details Charge sharing reduction by applying intrinsic parallelism... Charge sharing reduction by applying intrinsic parallelism...

2006-08-22

2006-08-22

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S093000, C326S094000, C326S095000, C326S096000, C326S097000, C326S098000, C326S112000, C326S119000, C326S121000

Reexamination Certificate

active

07095252

ABSTRACT:
The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.

REFERENCES:
patent: 6087855 (2000-07-01), Frederick et al.
patent: 6570408 (2003-05-01), Nowka
patent: 6667637 (2003-12-01), Mikan, Jr.
patent: 6914453 (2005-07-01), Dhong et al.
patent: 2003/0034801 (2003-02-01), Nowka
patent: 2005/0083082 (2005-04-01), Olofsson

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