Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-01-20
2001-01-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S086000, C326S087000, C326S088000, C326S082000, C326S090000, C326S092000
Reexamination Certificate
active
06172528
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to fanout buffers. More particularly, the present invention relates to fanout buffers designed to provide multiple synchronized outputs. Still more particularly, the present invention is a charge sharing circuit coupleable to a fanout buffer so as to ensure output synchronization.
2. Description of the Prior Art
Electronic circuit buffers are used to isolate load circuitry from affecting the operation of circuitry designed to control the load circuitry. That is, they provide an interface between a driving circuit and the circuitry being driven. The buffer is designed to ensure that signals are delivered from driving circuitry to one or more loads when required. Fanout buffers in particular are designed to isolate multiple output circuits from one or more input circuits. In most instances, fanout buffers are used to transfer a single logic (digital) signal from a logic circuit to a plurality of output loads coupled in parallel.
It can be seen that there are many possibilities for the application of fanout buffers. One sort of fanout buffer commonly used in computing systems is the clock buffer. A fanout clock buffer supplies a single timing signal to a plurality of load circuits. A clock timing signal is delivered to the fanout buffer which in turn supplies that timing signal to any number of loads, including, but not limited to, registers, memory, downstream circuit interfaces, and external peripherals. Ideally, in high-speed data transmission systems in particular, the buffer is designed such that all of the fanned out signals leave the clock driver synchronized, whether or not downstream intentional skewing is imparted to particular signals. Signal synchronization from the fanout buffer ensures that multiple computing tasks are properly coordinated. In high speed systems it also ensures that data transmission rates are properly coordinated for signal recognition purposes.
Unfortunately, in reality, fabrication vagaries, and temperature and load differences, among other reasons, cause uneven fanout signal skewing. That is, the signal transmitted from the buffer may be received more quickly by one load than another. Variations in signal transmission rates can cause significant task coordination problems, as well as data loss, both occurrences that are preferably avoided. It is therefore of value to provide a fanout buffer that can ensure signal synchronization.
Attempts at resolving this problem have met with some success. One solution involves tying together all of the output nodes of the fanout buffer such that the vagaries associated with one node are shared by all. However, such hardwiring can create adverse conditions in that all nodes will share a disruption applied to one node. In particular, a direct current path for all buffer outputs can be developed such as when one node is subject to a DC short. In that case, one short has the potential to overload all of the output nodes tied to that shorted node. This can occur, for example, in a backplane interface when a circuit board is inserted into a powered-up system and a short is generated by that live insertion. All boards coupled to that interface, which are in turn coupled to a fanout buffer, will experience the short. Given the potential hazard associated with a DC pathway, the simple tying together of fanout buffer circuits is an inadequate solution to skewing problems.
Other solutions that have been considered include the skew-minimizing circuit disclosed by Lim et al. in U.S. Pat. No. 5,481,209. Lim describes the application of tributary whiskers to distribute output loading. Some capacitive coupling is provided; however, the focus is on use of a tributary system that is organized to distribute signals to loads at various distances from an originating ring. The apparent goal of the Lim circuit is to equalize the distance between various loads and clock interfaces. Capacitive regulation may or may not be used to tune specific tributaries. The Lim circuit does not address fabrication and temperature vagary problems. It is to be noted that the capacitive effect of the whiskers is of concern in relatively fast switching (edge rates) systems, such as the fast switching fanout buffer that is the focus of the present invention. Circuitry with slower edge rates may not be concerned with the capacitive effects of these whiskers. The Lim circuitry must be tailored for every unique loading configuration in order to develop uniform edge rates. That may require changes in circuit timing and/or layout modifications. It thus lends itself to increased susceptibility to timing problems. In any event, the application of the customized tributary whiskers associated with the distribution ring take up valuable semiconductor board space.
The prior art of note fails to describe circuitry that provides acceptable and reliable synchronization of fanout buffer output signals. It is to be noted that prior attempts at output deskewing have been related to the use of relatively complex active transistor circuitry. Any reference to capacitive load sharing has been principally directed to that as a secondary feature of the active circuitry.
What is needed is a circuit that provides fanout synchronization. What is also needed is such circuitry that eliminates the hazards associated with DC shorts caused by linkage of all buffer outputs together. What is also needed is a fanout synchronization circuit that is relatively simple to form and that takes up a relatively small amount of board layout space.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a circuit that synchronizes fanout buffer output signals. It is also an object of the present invention to provide such circuitry without creating DC shorts or any other sort of output signal linking to the deleterious effects caused by vagaries associated with one or more of the buffer output nodes. Finally, it is an object of the present invention to provide fanout synchronization circuitry that is relatively simple to form and that takes up a relatively small amount of board layout space.
These and other objectives are achieved in the present invention through the introduction of sub-circuitry that is coupleable to existing fanout buffer output nodes of the type commonly used in the transmission, reception, and conversion of data, information, etc., moving from one location to another. The sub-circuitry of the present invention includes a capacitive element coupled to each output node of the fanout buffer. Each of those capacitive elements is linked together by way of a common bus. That common bus is preferably a floating bus in that it is not tied to any power pin, including either the high-potential power rail or the low-potential power rail of the system.
Using a floating bus as the common link ensures that DC shorts will not be developed across all buffer outputs. In addition, by not coupling the capacitive elements to the low-potential rail (ground) those elements will not act as a load on the buffer. A coupling to the power rails increases the problems associated with noise and jitter, including propagation and timing variations. Further, it is preferable to avoid additional output loading caused by coupling to the power rails in that it reduces the resultant power drain, increased heat, and reduced reliability associated therewith. This is of particular concern for low-power systems including, but not limited to, laptop computers for example.
The coupling of the capacitive elements, which may simply be capacitors or any other suitable charge regulator, to the common bus creates a homogenizing manifold. Specifically, faster individual output signals are slowed and slower signals are accelerated such that each output, at a point beyond its respective capacitive element, produces the same signal rate as all of the other buffer outputs. In effect, the faster signals act to charge through the common bus the capacitive elements of the nodes associated with slower signals.
The capacitive c
Atwood Pierce
Caseiro Chris A.
Fairchild Semiconductor Corporation
Tan Vibol
Tokar Michael
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