Charge shared match line differential generation for CAM

Details Charge shared match line differential generation for CAM Charge shared match line differential generation for CAM

2001-02-13

2002-01-29

Phan, Trong (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S203000

Reexamination Certificate

active

06343029

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a content addressable memory (CAM), particularly to power consumption management of the CAM.
BACKGROUND
In a conventional CAM, a match line (ML) changes its voltage level to indicate data mismatches. Typically, the ML is pre-charged to a given voltage level Vc. Then, the ML is discharged to ground in response to one or more data mismatches, wherein the voltage level of the ML drops from Vc by an amount referred to as the ML's “voltage swing.” In turn, this ML swing is detected by a sense amplifier to indicate the data mismatches. However, the CAM consumes a significant portion of its power to recover from this ML swing such that the ML's voltage level is again restored back to Vc. Moreover, the ML swing increases as the number of data mismatches increases.
Specifically, a ML consumes significant power due to it large voltage swing, high capacitance of CAM cells and high speed of operation. Unfortunately, conventional techniques to reduce power using lower voltage of operation or NAND configuration of CAM cells have limited advantages in term of speed. Moreover, the ML's swing depends on the number of cells causing in parallel a discharge of the ML. As such, even with a minimum number of cells discharging the ML, limiting the ML's swing actually causes a significant speed degradation.
Thus, a need exists for a CAM whose ML power consumption can be reduced. Specifically, a need exists for limiting a CAM's ML swing. A need also exists for limiting the ML swing irrespective of the number of cells discharging the ML in parallel while not causing significant speed degradation.
SUMMARY
The invention is drawn to a content addressable memory (CAM) with built-in power saving management. Specifically, the invention provides a CAM that limits its match line (ML) voltage swing while not causing significant speed degradation. Also, the invention provides a CAM that limits the ML voltage swing irrespective of the number of cells discharging the ML in parallel.
In one embodiment, the CAM includes a comparator circuit region that is coupled to a ML as well as a swing line (SL). The comparator circuit region is also coupled to CAM cells. The comparator region is adapted for comparing match data with stored data within the CAM cells. The ML has its ML voltage level pre-charged to a certain voltage level (Vc). Additionally, the SL is pre-charged to ground. In turn, in response to a data mismatch detected by the comparator, the ML voltage level drops from Vc by a ML voltage swing (Vswing). In response to this data mismatch, the SL charge shares with the ML such that this Vswing is less or equal to Vc/2. That is, the charge sharing prevents the ML from discharging all the way to ground. Thus, Vswing is as large as about Vc/2 in the invention, whereas Vswing is as large as V in a conventional CAM. Thus, in comparison to a conventional CAM, the present invention requires less than half of the power required to recover from a voltage swing of the ML. As such, advantageously, the invention's Vswing restriction (through charge sharing technique) provides significant power saving in comparison to a conventional CAM.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various figures.


REFERENCES:
patent: 5617348 (1997-04-01), Maguire
patent: 6181591 (2001-01-01), Miyatake et al.
patent: 6240001 (2001-05-01), Ross

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