Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-05-31
2002-01-15
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S185280
Reexamination Certificate
active
06339557
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of Japanese Patent Application No. 11-154798 filed on Jul. 2, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a reliability test, and particularly relates to a charge retention lifetime evaluation method for a nonvolatile semiconductor memory.
2. Description of the Related Art
FIG. 8
shows an example of anonvolatile semiconductor memory such as a flash memory or an EPROM. Memory cells
100
are arranged in a matrix. Each memory cell
100
constitutes several bits.
FIG. 9
shows a basic constitution of each memory cell
100
.
In the memory cell
100
, a source region
21
and a drain region
22
are provided in a surface portion of a semiconductor substrate
20
separately from each other. A floating gate electrode
24
is disposed above the semiconductor substrate
20
between the regions
21
and
22
through a tunnel film
23
. Further, a control gate electrode
26
is disposed above the floating gate electrode
24
through an insulating film
25
interposed therebetween. The drain region
22
is connected to a bit line, the source region
21
is connected to a source line, and the control gate electrode
26
is connected to a word line.
To read data in the memory cell, as shown in
FIG. 9
, a positive voltage of 1 to 2 V is applied to the drain region
22
, the source region
21
is grounded, and voltage Vcc is applied to the control gate electrode
26
. Accordingly, it is detected whether a channel current flows or not.
To write data in the memory cell, as shown in
FIG. 10
, voltage Vcc (for instance 5.5 V) is applied to the drain region
22
, the source region
21
is grounded, and high voltage Vpp (for instance, +12 V) is applied to the control gate electrode
26
. Accordingly, hot electrons are generated around the drain region
22
, and are injected into the floating gate electrode
24
to increase a threshold voltage of the memory cell.
To erase data, as shown in
FIG. 11
, high positive voltage Vpp (for instance, +12 V) is applied to the source region
21
, and the control gate electrode
26
is grounded. Accordingly, electrons are extracted from the floating gate electrode
24
into the source region
21
. At that time, the drain region
22
is opened. Alternatively, electrons may be extracted from the floating gate electrode
24
into the substrate
20
due to a tunnel effect as shown in FIG.
12
. In
FIG. 12
, a negative high voltage (for instance, −8 V) is applied to the control gate electrode
26
, and a high positive voltage (for instance, +10 V) is applied to both the source region
21
and the substrate
20
.
This type of nonvolatile semiconductor memory is evaluated by reliability tests. One such test is a charge retention lifetime evaluation test (memory holding time test). A flash memory is, for instance, required to have high charge retention characteristics of more than 10 years at 125° C. Therefore, evaluating the charge retention lifetime requires a long time even at a development stage, and a very high evaluation ambient temperature accelerates the evaluation speed.
However, there is a case where the evaluation ambient temperature cannot be set so high. In addition, when the charge retention lifetime is evaluated at approximately 250° C. or more after rewriting, damage caused to the tunnel film (film
23
in
FIG. 9
) by rewriting is recovered to prevent the charge retention lifetime from being evaluated accurately. That is, the accelerated heating accompanied by the recovery of tunnel film damage is not preferable for charge retention lifetime evaluation purposes.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problems. A first object of the present invention is to provide a method for evaluating a charge retention lifetime of a nonvolatile semiconductor memory for a short time regardless of an evaluation ambient temperature. A second object of the present invention is to provide a method for evaluating a charge retention lifetime of a nonvolatile semiconductor memory for a short time accurately.
In a charge retention lifetime evaluation method for a nonvolatile semiconductor memory according to the present invention, a charge retention lifetime is evaluated by externally applying a tunnel film voltage to a tunnel film. Therefore, the charge retention lifetime can be evaluated for a short time due to an accelerated evaluation, in which the voltage is intentionally applied to the tunnel film.
Preferably, first and second voltages different from each other are applied as the tunnel film voltage, and the charge retention lifetime when no voltage is externally applied to the tunnel film is estimated. The tunnel film voltage is preferably smaller than a voltage applied to the tunnel film at each operation for reading, writing, and erasing.
Preferably, an electric potential of a control gate electrode is set to be lower than that of a semiconductor substrate so that the tunnel film voltage is applied to the tunnel film. More preferably, a negative voltage is applied to the control gate electrode while making the semiconductor substrate grounded.
The charge retention lifetime can be evaluated in a temperature range at which damage generated in the tunnel film for writing data is not recovered. Accordingly, the charge retention lifetime can be evaluated for a short time accurately.
The charge retention lifetime can be evaluated in an operational temperature range at which the nonvolatile semiconductor memory is used in practice. Accordingly, the charge retention lifetime can be evaluated for a short time accurately. In this case, it is more preferable for a practical use to apply the voltage to the tunnel film at the maximum temperature in the operational temperature range.
REFERENCES:
patent: 5279981 (1994-01-01), Fukatsu et al.
patent: 5541129 (1996-07-01), Tsunoda
patent: 5636168 (1997-06-01), Oyama
patent: 5864501 (1999-01-01), Lee
patent: 5901080 (1999-05-01), Shaino
patent: 6002609 (1999-12-01), Shinada
patent: 6054351 (2000-04-01), Sato et al.
patent: 6-60700 (1994-03-01), None
patent: 8-138390 (1996-05-01), None
patent: 9-027198 (1997-01-01), None
patent: 9-097500 (1997-04-01), None
patent: 9-260613 (1997-10-01), None
patent: 11-204664 (1999-07-01), None
patent: 11-284040 (1999-10-01), None
patent: 11-306772 (1999-11-01), None
patent: 11-306773 (1999-11-01), None
Katsumata et al., “Reliability evaluation of thin gate oxide using a flat capacitor test structure,” Technical report of IEICE, SDM95-26 (May 1995), pp. 49-53.
Nozawa et al., “A thermionic electron emission model for charge retention in SAMOs structures,” Japanese journal of applied physics, vol. 21, No. 2, (Feb., 1982), pp. L111-L112.
Fukatsu Shigemitsu
Katada Mitsutaka
Kawaguchi Tsutomu
Denso Corporation
Elms Richard
Law Office of David G. Posz
Phung Anh
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