Static information storage and retrieval – Read/write circuit – Including signal clamping
Patent
1989-12-19
1993-02-09
Bowler, Alyssa H.
Static information storage and retrieval
Read/write circuit
Including signal clamping
365149, 36518911, 365203, 365204, 3072965, G11C 700, G11C 11413, G11C 514
Patent
active
051857219
ABSTRACT:
During an active phase of operation of the circuit (70), a gate (38) of a transistor (14) is boosted to a first voltage level that is substantially above the voltage supply level (V.sub.dd). After the gate (38) is boosted, the signal node (12) is boosted by transmitting current through the current path of the transistor (14) from a first electrode (16) of a boosting capacitor (18). During a reset phase of operation of the circuit (70), a second electrode (26) of the capacitor (18) is discharged. This causes the withdrawl of the charge from the signal node (12) through the current path of the transistor (14) to the first electrode (16) of the boosting capacitor (18). A predetermined voltage level near the voltage supply level is established across the electrodes (16, 26) of the boosting capacitor (18) in response to this. Finally, the transistor gate (38) is discharged to isolate the boosting capacitor (18) from the node (12 ), such that the desired voltage level is maintained across the boosting capacitor (18) for an extended length of time.
REFERENCES:
patent: 3623031 (1971-11-01), Kumada
patent: 3942047 (1976-03-01), Buchanan
patent: 4149232 (1979-04-01), Eaton, Jr.
patent: 4404661 (1983-09-01), Nagayama et al.
patent: 4455493 (1984-06-01), Murton et al.
patent: 4503522 (1985-03-01), Etoh et al.
patent: 4583157 (1986-04-01), Kirsch et al.
patent: 4636981 (1987-01-01), Ogura
patent: 4638182 (1987-01-01), McAdams
patent: 4677313 (1987-06-01), Mimoto
patent: 4703196 (1987-10-01), Arakawa
patent: 4707625 (1987-11-01), Yanagisawa
patent: 4736121 (1988-04-01), Cini et al.
patent: 4763301 (1988-08-01), Schuetz
patent: 4769792 (1988-09-01), Nogami et al.
patent: 4787066 (1988-11-01), Leuschner
patent: 4788664 (1988-11-01), Tobita
patent: 4792928 (1988-12-01), Tobita
patent: 4831257 (1989-05-01), McClelland et al.
patent: 4878201 (1989-10-01), Nakaizumi
patent: 4896297 (1990-01-01), Miyatake et al.
patent: 4916334 (1990-04-01), Minagawa et al.
patent: 4954731 (1990-09-01), Dhong et al.
patent: 5012445 (1991-04-01), Kazuaki et al.
IBM-TDB-vol. 28, No. 6,; Nov. 1985 "Simple Word Line Boosting Circuit for High Performance CMOS DRAM's".
Kersh, III David V.
Love Andrew M.
Bowler Alyssa H.
Donaldson Richard L.
Kesterson James C.
Neerings Ronald O.
Texas Instruments Incorporated
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