Charge-redistribution low-swing differential logic circuit

Details Charge-redistribution low-swing differential logic circuit Charge-redistribution low-swing differential logic circuit

2000-10-05

2001-12-18

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C326S095000, C326S086000, C326S083000, C327S055000, C327S057000, C365S205000

Reexamination Certificate

active

06331791

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a differential logic circuit, and more particularly to a charge-redistribution low-swing differential logic circuit.
2. Description of the Related Art
For a current logic system, especially in design for a complicated high-speed circuit, a differential logic circuit is adopted in order to achieve both true signal and its complementary signal. For example, as shown in
FIG. 1
, in U.S. Pat. No. 4,570,084, this logic system comprises logic networks
10
and
12
each acting as a switch so that when logic network
10
is closed, logic network
12
is open. Input signal INPUTS and its complementary signal COMPLEMENTARY INPUTS are applied to logic networks
10
and
12
, respectively, for controlling its switching operation in networks
10
and
12
. Network
10
is connected between an output node
14
and a NMOS pull down transistor
16
connected to ground. Network
12
is connected between an output node
18
and a NMOS pull down transistor
20
connected to ground. A clock pulse &phgr;
c
is applied to the control of whether or not the transistors
16
and
20
are active.
A load circuit
22
comprises PMOS transistors
24
and
26
connected between a source of potential Vdd and output node
14
, and PMOS transistors
28
and
30
connected between source Vdd and output node
18
. An inverter
32
is connected between an output Q and output node
14
. An inverter
34
is connected between a complementary output terminal {overscore (Q)} of terminal Q and output node
18
. Also, clock&phgr;
c
is applied to the control of whether or not the transistors
24
and
28
are active.
In the operation of precharging and equalizing, clock&phgr;
c
is at a potential level of logic 0. This turns off NMOS transistors
16
and
20
and turns on PMOS transistors
24
and
28
. Therefore output node
14
and
18
are precharged to source Vdd. At this time, both output terminals Q and {overscore (Q)} are at logic 0 level through corresponding inverters
32
and
34
. As a result, PMOS transistors
26
and
30
are turned on in order to maintain the conductive state.
In the operation of evaluating the information provided by the complementary input signals INPUTS and COMPLEMENTARY INPUTS of its associated logic networks
10
and
12
, clock&phgr;
c
is at a potential level of logic 1. This turns on NMOS transistors
16
and
20
and turns off PMOS transistors
24
and
28
. Because network
10
is closed, output node
14
is effectively grounded. Because network
12
is open, output node
18
is prevented from discharging so as to maintain at logic 1 level. At this time, output terminal Q is at logic 1 level through inverter
32
and output terminal {overscore (Q)} is at logic 0 level through inverter
34
. As a result, PMOS transistor
26
is maintained in an off condition, and PMOS transistor
30
is maintained in an on condition.
In the foregoing conventional art, the complementary output signal pair are obtained by the differential logic circuit at the same time; additionally, its full swing is from source Vdd to ground Vss.
In current SRAM or DRAM applications, a sense amplifier is often used to detect and amplify an input signal pair; for example an input signal pair from a bit line and its complementary bit line, which have a slight voltage difference, such as a difference of about 100 mV.
Hereinafter, the schematic diagrams of FIG.
2
through
FIG. 6
are used to depict the corresponding prior art applications.
Referring to
FIG. 2A
, as described in U.S. Pat. No. 4,843,264, a sense amplifier is used to rapidly amplify the difference between input signal IN and its complementary input signal INB. In the configuration of
FIG. 2A
, input signal pair IN and INB are coupled to two NMOS sensing transistors M
5
and M
6
. A latch is formed by two cross coupled CMOS inverters M
1
-M
3
and M
2
-M
4
, wherein a common gate input G
1
of M
2
and M
4
are coupled to node n
1
, which is formed by the source-drain series connection of M
1
and M
3
, thereby providing a complementary output signal OUTB. Likewise, a common gate input G
2
of M
1
and M
3
are coupled to node n
2
which is formed by the source-drain series connection of M
2
and M
4
, thereby providing an output signal OUT. Nodes n
3
and n
4
couple the sources of the NMOS pull down transistors M
3
and M
4
to the drains of the NMOS sensing transistors M
5
and M
6
, respectively. Pull down transistor M
7
is activated when sensing is to be performed.
Referring to
FIG. 2B
, a sense amplifier combining with precharging and equalizing circuitry is illustrated. During precharging, since PMOS transistors M
13
, M
14
, and M
17
constitute a precharge circuit and equalizing signal EQB is at logic 0 level, transistors M
13
, M
14
, and M
17
are turned on, which will consequently activate nodes n
1
, n
2
being precharged by equalizing signal EQB to Vdd and so equalized. Likewise, PMOS transistors M
18
, M
19
, and M
20
also constitute a precharge circuit, therefore nodes n
3
, n
4
are precharged by equalizing signal EQB to Vdd and so equalized. Further, during sensing, equalizing signal EQB is at logic 1 level, which will consequently disable two precharge circuits, then transistor M
7
is turned on by control signal SE to pull down the potential on node n
5
. Assume that the voltage on signal IN is 100 mV higher than the voltage on signal INB, thereby producing a current difference between transistor M
5
and transistor M
6
. The gate-to-source voltage of transistor M
5
is higher than that of transistor M
6
. As a result, when sensing begins, node n
3
will begin pulling down sooner than n
4
, and thus node n
1
will be pulled down faster than n
2
. Therefore, the potential on node
4
is higher compared to node
3
, and the potential on node
1
is lower compared to node
2
. Thus, transistor M
4
is less conductive than transistor M
3
because the gate-to-source voltage on M
4
(not shown in figure) will be decreased relative to the gate-to-source voltage on M
3
. The voltage on node n
2
will quickly rise back towards Vdd (OUT) with transistor M
4
beginning to shut down. Finally, the relatively high voltage on node n
2
will keep transistor M
1
off reinforcing the rate at which node n
1
is pulled down to Vss (OUTB).
Accordingly, only a small voltage difference is required for detecting an input signal pair. For example, as the voltage on signal IN is 100 mV higher than the voltage on signal INB, two cross coupled CMOS inverters M
1
-M
3
and M
2
-M
4
, which form a latch, will rapidly amplify the signal differential between signal IN and INB, and to thereby latch the sensed voltages into nodes n
1
and n
2
as signals Vss and Vdd, where nodes n
1
and n
2
constitute a complementary signal pair labeled OUTB and OUT.
Moreover, because one of the two devices on each of the latch (two cross coupled CMOS inverters M
1
-M
3
and M
2
-M
4
) will be off, either the pull up transistor (M
1
or M
2
) or the pull down transistor (M
3
or M
4
) will be off on each side of the latch. Thus, after the same amplifier has latched, it consumes no d.c. power. The foregoing techniques provide the advantages of low power consumption, high speed operation, and sense amplifier outputting full swing from power Vdd to ground Vss.
Referring to
FIG. 3A
, which is another sense amplifier
9
as described in U.S. Pat. No. 4,910,713. Comparing sense amplifier
9
of
FIG. 3A
to the one in
FIG. 2A
, the main difference of both is that two sensing transistors exchange the positions with two lower NMOS transistors of the latch.
An input signal pair
15
,
17
of a sense amplifier
9
are coupled to NMOS sensing transistors N
4
and N
5
. A latch is formed by two cross-coupled CMOS inverters
11
,
13
. Inverter
11
with a common gate input G
1
comprises a PMOS pull up transistor P
2
and a NMOS pull down transistor N
1
both coupled in series by a NMOS sensing transistor N
4
. The common gate input G
1
of inverter
11
is coupled to an output node
25
, which is a

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