Charge recycling differential logic (CRDL) circuit and storage e

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor

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326121, H03K19/096

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active

059031697

ABSTRACT:
A storage element for a semiconductor device in accordance with preferred embodiments exhibit less noise and consumes less power with faster speed. A first circuit maintains a first storage node at a same signal level of a previous state when an input signal at an input electrode transits from one of (i) first signal level to second signal level and (ii) third signal level to second signal level. The first circuit includes a first plurality of transistors coupled to the input electrode, and a first pair of transistors coupled to said first plurality of transistors and coupled to each other at the first storage node. A second circuit, coupled to said first circuit, changes a condition of said first storage node to one of (i) first signal level when the input signal transits from the second signal level to the first signal level and (ii) third signal level when the input signal transits from the second signal level to the third signal level.

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