Charge recovery logic including split level logic

Details Charge recovery logic including split level logic Charge recovery logic including split level logic

1993-08-03

1995-01-03

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326121, 326 98, 327199, H03K 1900

Patent

active

053789407

ABSTRACT:
In a pipelined logic circuit, switches are only enabled when voltage differentials across the switches are zero. The switches are configured during a restored state of voltage rails, and a swing in voltage on the rails results in a swing in output voltage to a set level. To restore the logic circuit with minimal energy dissipation and permit useful pipelining, the inputs are regenerated through an inverse logic circuit. The voltage rail then swings back to its restored level. Full forward and reverse pipelines are formed with the individual forward and inverse logic circuits with the pipelines being driven by multiphase clock rails. Each logic stage includes a logic gate and a pass gate.

REFERENCES:
Mead and Conway,Introduction to VLSI Systems, Addison-Wesley Publishing Co., Reading, Mass., Oct. 1980, pp. 348-351.
Younis, Saed G. et al., "Practical Implementation of Charge Recovering Asymptotically Zero Power CMOS," Artificial Intelligence Laboratory, Massachusetts Institute of Technology, presented for publication, pp. 1-17.
Fredkin, E., and Toffoli, T., (1978), "Design Principles for Achieving High-performance Submicron Digital Technologies," Proposal to DARPA, MIT Laboratory for Computer Science.
Koller, J. G., and Athas, W. C., "Adiabatic Switching, Low Energy Computing, and the Physics of Storing and Erasing Information," in Proceedings of Physics of Computation Workshop, Dallas, Texas, Oct. 1992, pp. 1-5.
Merkle, R. C., "Reversible Electronic Logic Using Switches," Submitted to Nanotechnology, 1992, pp. 1-31.
Hall, J. S., "An Electroid Switching Model for Reversible Computer Architectures," in Proceedings of Physics of Computation Workshop, Dallas, Texas, Oct. 1992.
Seitz, Charles L. et al., "Hot-Clock nMOS," in Proceedings of the 1985 Chapel Hill Conference on VLSI, Computer Science Press, 1985.
Margolis, Norm, Ph.D. Thesis, Physics, Jun. 1987.

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