Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2001-08-16
2003-05-27
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S088000, C327S589000
Reexamination Certificate
active
06570408
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to dynamic logic circuits, and more particularly to dynamic logic circuits having circuitry for reduced power consumption.
2. Related Art
Due to its speed, it is well known to use dynamic circuitry for high-performance applications.
FIG. 1
illustrates a prototypical prior art dynamic logic circuit
100
. The circuit
100
has a dynamic node
150
which is precharged to a high voltage during a precharge phase timed by clock
115
. Then during an evaluation phase, also timed by clock
115
, the dynamic node
150
may be selectively pulled down to a low voltage through input circuitry
122
, depending on the state of the inputs.
More specifically, during the phase of clock
115
when the clock signal is low, PFET
101
in timing circuitry
120
is turned on and NFET
108
is turned off, which pulls dynamic node
150
up to Vdd. Then during the evaluation phase, that is, during the phase of clock
115
when the clock signal is high, PFET
101
is turned off and NFET
108
is turned on, so that the dynamic node
150
may be selectively pulled down to a low voltage through the NFET's
110
through
107
of input circuitry
122
, depending on the state of the inputs on the gates
110
through
113
.
The dynamic circuit
100
of
FIG. 1
is a “domino” type of dynamic circuit, which includes an output stage, output circuitry
124
that enables chaining a number of dynamic circuits in series, or series-parallel combinations. That is, output circuitry
124
is a static gate which converts the state of the dynamic node
150
so that when the dynamic node
150
is in the precharged state the output signal on node
114
is low. Thus, even if the foot FET
108
is omitted in the next stage, the output
114
may be an input to a next dynamic logic circuit in a series without interfering in the precharging of the dynamic node in the next dynamic logic circuit.
The dynamic circuit
100
also has keeper circuitry
126
coupled to the output
114
, Vdd, and the dynamic node
150
for keeping the dynamic node at the precharged state during the evaluation phase despite leakage through the input circuitry
122
and the foot device
108
if none of the inputs are active.
Conventionally, dynamic logic circuits have not been as widely used as have static logic circuits in applications requiring low-power consumption. However, there is a current trend requiring higher performance for embedded processors in applications such as personal digital assistants, cell phones, electronic books, watches, etc. This is particularly brought on by the demand for rendering of images by such devices, such as for Internet browsers. The embedded processors in these applications are frequently battery powered, so there is an increasing need for reduced power consumption in dynamic logic circuits.
SUMMARY OF THE INVENTION
The foregoing need is addressed in the present invention, according to which a dynamic circuit includes charge recovery circuitry for controlling the circuitry to reduce power consumption.
More particularly, the dynamic circuit includes a dynamic node and precharge timing circuitry coupled to the dynamic node and to a voltage source for driving the node to a high voltage state during a precharge interval responsive to a precharge signal. The dynamic circuit also includes input circuitry coupled to the dynamic node for selectively discharging the dynamic node to a low voltage state during an evaluation interval responsive to one or more input signals. Charge recovery circuitry of the dynamic circuit has a capacitor and circuitry for controlling transfer of charge from the dynamic node to the capacitor during the evaluation time interval and from the capacitor back to the dynamic node during the pre charge time interval.
In a method form, a method for charge recovery in dynamic circuitry includes discharging a charge from a dynamic node during an evaluation interval by input circuitry coupled to the dynamic node responsive to one or more input signals. The discharging includes transferring the charge from the dynamic node to a capacitor during the evaluation time interval. Then, during a precharge interval the dynamic node is charged to a higher voltage state by precharge timing circuitry coupled to the dynamic node and to a voltage source responsive to a precharge signal. The charging includes transferring the charge from the capacitor to the dynamic node during the precharge interval.
In an alternative method form, the method includes discharging a charge from a dynamic node of a first dynamic circuit during an evaluation interval by input circuitry for the dynamic circuit. The discharging includes transferring the charge from the dynamic node of the first dynamic circuit, by charge recovery circuitry, to a dynamic node of a predecessor dynamic circuit during the evaluation time interval of the first dynamic circuit. The dynamic node of the first dynamic circuit is charged to a higher voltage state during a precharge interval of the first dynamic circuit by precharge timing circuitry for the first dynamic circuit. The charging includes transferring charge from the dynamic node of the a successor dynamic circuit to the dynamic node of the first dynamic circuit during the precharge interval for the first dynamic circuit.
The present invention is advantageous because by recovering charge in the circuitry power consumption is reduced. Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.
REFERENCES:
patent: 5642061 (1997-06-01), Gorny
patent: 5859548 (1999-01-01), Kong
patent: 5910735 (1999-06-01), Allen
patent: 6373290 (2002-04-01), Forbes
Cho James H
England Anthony V. S.
International Business Machines - Corporation
Salys Casimer K.
LandOfFree
Charge recovery for dynamic circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Charge recovery for dynamic circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charge recovery for dynamic circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3061135