Charge-pumping circuit for semiconductor memory device

Details Charge-pumping circuit for semiconductor memory device Charge-pumping circuit for semiconductor memory device

1996-09-13

1998-06-30

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327537, 327589, G05F 110

Patent

active

057740127

ABSTRACT:
A charge-pumping circuit of a semiconductor memory device for generating a voltage higher than an applied supply voltage, including a first MOS transistor having gate and drain terminals through which the supply voltage is received and a source terminal through which an initial voltage is provided to a first node; a first capacitor with predetermined capacitance having one plate connected to the first node and the other plate through which an applied first oscillating signal is received; a third MOS transistor having gate and source terminals connected to the first node to introduce the electric current of the first node into its drain terminal; a second capacitor with capacitance lower than that of the first capacitor, having one plate connected to the second node that is the drain terminal of the third MOS transistor and the other plate through which an applied second oscillating signal is received; and a second MOS transistor having drain and gate terminals connected to the first node and the second node each and a source terminal connected to an output terminal so as to apply the voltage of the first node to the output terminal in response to the voltage of the second node.

REFERENCES:
patent: 5140182 (1992-08-01), Ichimura
patent: 5180928 (1993-01-01), Choi
patent: 5386151 (1995-01-01), Folmsbee
patent: 5394372 (1995-02-01), Tanaka et al.
patent: 5561385 (1996-10-01), Choi
patent: 5589793 (1996-12-01), Kassapian

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